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? 2001 microchip technology inc. preliminary ds41171a pic16c781/782 data sheet 8-bit cmos microcontrollers with a/d, d/a, opamp, comparators and psmc
ds41171a - page ii preliminary ? 2001 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are reg- istered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filter- lab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picc, picdem, picdem.net, icepic, migratable memory, fansense, economonitor, select mode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2001 microchip technology inc. preliminary ds41171a-page 1 pic16c781/782 microcontroller core features: high performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two cycle direct, indirect and relative addressing modes - operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 8-level deep hardware stack interrupt capability (up to 8 internal/external interrupt sources) 16 i/o pins: - individual direction control (13 pins) - input only (3 pins), low leakage (2 pins) - digital/analog inputs (8 pins) programmable portb interrupt-on-change (8 pins) programmable portb weak pull-ups (8 pins) power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with a software enabled option and its own on-chip rc oscillator for reliable operation programmable brown-out reset (bor) programmable low voltage detection (lvd) internal/external mclr programmable code protection power saving sleep mode selectable oscillator options: hs, xt, lp, ec, rc, intrc (4 mhz/37 khz) in-circuit serial programming ? (iscp ? ) program memory read (pmr) capability four user programmable id locations wide operating voltage range: - 2.5v to 5.5v for commercial and industrial temperature ranges - extended temperature range available microcontroller core features (continued): low power, high speed cmos eprom technology fully static design low power consumption: - < 2ma @ 5v, 4mhz -< 1 a typical standby current. pin diagram peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - option to use osc1 and osc2 in lp mode as timer1 oscillator, if intrc oscillator mode selected analog-to-digital converter (adc): - 8-bit resolution - programmable 8-channel input - internal voltages available for self- diagnostics digital-to-analog converter (dac): - 8-bit resolution - reference from av dd , v ref 1, or v r module - output configurable to v dac pin, compara- tors, and adc reference operational amplifier module (opa): - firmware initiated input offset voltage auto calibration module - low leakage inputs - programmable gain bandwidth product (gbwp) device program memory x14 data memory x8 pic16c781 1k 128 PIC16C782 2k 128 pdip, windowed cerdip, soic, ssop rb3/an7/opa rb2/an6 ra6/osc2/clkout/t1cki v dd rb7/c2/psmc1b/t1g rb6/c1/psmc1a rb5 rb4 ra7/osc1/clkin ra0/an0/opa+ ra1/an1/opa- ra5/mclr /v pp v ss av ss ra2/an2/v ref 2 ra3/an3/v ref 1 rb0/int/an4/v r ra4/t0cki rb1/an5/v dac av dd 2 3 4 5 6 7 8 9 10 1 19 18 16 15 14 13 12 11 17 20 pic16c781/782 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 8-bit cmos microcontrollers with a/d, d/a, opamp, comparators and psmc
pic16c781/782 ds41171a-page 2 preliminary ? 2001 microchip technology inc. peripheral features (continued): dual analog comparator module with: - individual enable and interrupt bits - programmable speed and output polarity - fully configurable inputs and outputs - reference from dac, or v ref 1/v ref 2 - low input offset voltage. v r voltage reference module: - 3.072v +/- 0.7% @25 c, av dd = 5v - configurable output to adc reference, dac reference, and v r pin - 5 ma sink/source programmable switch mode controller module: - pwm and psm modes - programmable switching frequency - configurable for either single or dual feedback inputs - configurable single or dual outputs - slope compensation output available in single output mode key features picmicro ? mid-range reference manual (ds33023) pic16c781 PIC16C782 operating frequency dc - 20 mhz dc - 20 mhz resets (and delays) por, bor, mclr , wdt (pwrt, ost) por, bor, mclr , wdt (pwrt, ost) program memory (14 bit words) 1k 2k data memory (bytes) 128 128 interrupts 8 8 i/o ports 13 + 3 input only 13 + 3 input only timers 2 2 programmable switch mode controller 1 1 8-bit analog-to-digital module 1 1 adc channels 8 external, 2 internal 8 external, 2 internal 8-bit digital-to-analog module 1 1 comparators 2 2 comparator channels 4 (an<7:4>) 4 (an<7:4>) operational amplifier 1 1 voltage reference 1 1 brown-out reset yes yes programmable low voltage detect yes yes instruction set 35 instructions 35 instructions
? 2001 microchip technology inc. preliminary ds41171a-page 3 pic16c781/782 table of contents 1.0 device overview ............................................................................................................ ............................................................. 5 2.0 memory organization ........................................................................................................ ........................................................ 11 3.0 i/o ports .................................................................................................................. .................................................................. 25 4.0 program memory read (pmr) .................................................................................................. ................................................ 47 5.0 timer0 module .............................................................................................................. ............................................................ 51 6.0 timer1 module with gate control ............................................................................................ .................................................. 55 7.0 voltage reference module (v r ) ............................................................................................................................. ................... 61 8.0 programmable low voltage detect module (plvd) .............................................................................. ................................... 63 9.0 analog-to-digital converter (adc) module ................................................................................... ............................................ 69 10.0 digital-to-analog converter (dac) module .................................................................................. ............................................. 79 11.0 operational amplifier (opa) module ........................................................................................ ................................................. 83 12.0 comparator module ......................................................................................................... .......................................................... 89 13.0 programmable switch mode controller (psmc) ................................................................................ ....................................... 99 14.0 special features of the cpu ............................................................................................... ................................................... 117 15.0 instruction set summary ................................................................................................... ...................................................... 133 16.0 development support ....................................................................................................... ....................................................... 141 17.0 electrical characteristics ................................................................................................ ......................................................... 147 18.0 dc and ac characteristics graphs and tables ............................................................................... ....................................... 167 19.0 packaging information ..................................................................................................... ........................................................ 169 index .......................................................................................................................... ........................................................................ 175 on-line support................................................................................................................ ................................................................. 181 reader response ................................................................................................................ .............................................................. 182 pic16c781/782 product identification system .................................................................................... .............................................. 183 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the 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pic16c781/782 ds41171a-page 4 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 5 pic16c781/782 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro ? mid-range reference manual (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet. the reference manual is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. this data sheet covers two devices: pic16c781 and PIC16C782. both devices come in a variety of 20-pin packages. the following figures are block diagrams of the pic16c781 and the PIC16C782. figure 1-1: pic16c781 block diagram eprom program memory 1k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 128 x 8 direct addr 7 ram 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/ osc2/ v dd , v ss porta portb ra4/t0cki ra5/mclr /v pp rb0/int/an4/v r 8 8 reset note 1: av dd and av ss pins are used by the following modules: c1, c2, opa, dac, adc, and v r . 8-bit (psmc) opamp 8-bit adc timer0 comparator comparator ra3/an3/v ref 1 ra2/an2/v ref 2 ra1/an1/opa- ra0/an0/opa+ 8 3 clkout clkin ra6/osc2/clkout/t1cki ra7/osc1/clkin rb1/an5/v dac rb2/an6 rb3/an7/opa rb4 rb5 rb6/c1/psmc1a rb7/c2/psmc1b/t1g (c2) (c1) (v r ) module dac av dd , av ss (1) addr program memory read (pmr) (opa) low voltage detect brown-out internal rc programmable switch mode controller oscillator voltage reference (plvd) (tmr0) (tmr1) intrc programmable timer1
pic16c781/782 ds41171a-page 6 preliminary ? 2001 microchip technology inc. figure 1-2: PIC16C782 block diagram eprom program memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 128 x 8 direct addr 7 ram 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/ osc2/ v dd , v ss porta portb ra4/t0cki ra5/mclr /v pp rb0/int/an4/v r 8 8 brown-out reset note 1: av dd and av ss pins are used for the following modules: c1, c2, opa, dac, adc, and v r . 8-bit psmc opamp 8-bit adc timer0 comparator comparator ra3/an3/v ref 1 ra2/an2/v ref 2 ra1/an1/opa- ra0/an0/opa+ 8 3 clkout clkin ra6/osc2/clkout/t1cki ra7/osc1/clkin rb1/an5/vdac rb2/an6 rb3/an7/opa rb4 rb5 rb6/c1/psmc1a rb7/c2/psmc1b/t1g c2 c1 voltage reference (tmr1) dac av ss , av ss (1) addr program memory read (pmr) opa low voltage detect internal rc mode controller plvd module (v r ) timer1 tmr0 oscillator programmable intrc programmable switch
? 2001 microchip technology inc. preliminary ds41171a-page 7 pic16c781/782 figure 1-3: analog signal multiplexing diagram c1 c2 opa ra0/an0/opa+ ra1/an1/opa- ra2/an2/v ref 2 rb0/int/an4/v r rb1/an5/v dac rb2/an6 rb3/an7/opa ra3/an3/v ref 1 0 1 2 3 4 5 6 7 v r v dac an4 an5 an6 an7 v ref 1 v dac an4 an5 an6 an7 v ref 2 v dac en 0 1 0 1 2 3 0 1 0 1 2 3 0 1 0 1 2 av dd v ref 1 v r adc ref adc dac 0 1 2 av dd v ref 1 v r an4 v dac en 3 v dac 3 n/c an4 v r reference chs3 opaon gbwp chs<2:0> 3 vcfg<1:0> adon go/done chs0 2 c1ch<1:0> c1on c1sp c1pol c1out c1r 2 c2ch<1:0> c2r c2on c2sp c2pol c2out dars<1:0> 2 daon dac register 8 dac ref daon & daoe vroe & vren vren adres 8 cmpen rb6/c1/ c1oe rb7/c2 c2oe psmc1a psmc1b
pic16c781/782 ds41171a-page 8 preliminary ? 2001 microchip technology inc. table 1-1: pic16c781/782 pinout description name function input type output type description ra0/an0/opa+ ra0 st n/a port input an0 an ? adc input opa+ an ? opamp non-inverting input ra1/an1/opa- ra1 st n/a port input an1 an ? adc input opa- an ? opamp inverting input ra2/an2/v ref 2 ra2 st cmos bi-directional i/o an2 an ? adc input v ref 2an ? comparator 2 voltage reference input ra3/an3/v ref 1 ra3 st cmos bi-directional i/o an3 an ? adc input v ref 1an ? comparator 1, adc, dacref input ra4/t0cki ra4 st od bi-directional i/o tocki st ? timer0 clock input ra5/mclr /v pp ra5 st n/a port input mclr st ? master clear input v pp power ? programming voltage ra6/osc2/clkout/t1cki ra6 st cmos bi-directional i/o osc2 ? xtal crystal/resonator clkout ? cmos fosc/4 output t1cki st ? timer1 clock input ra7/osc1/clkin ra7 st cmos bi-directional i/o osc1 xtal ? crystal/resonator clkin st ? external clock input rb0/int/an4/v r rb0 ttl cmos bi-directional i/o int st ? external interrupt an4 an ? adc, comparator input v r ? an internal voltage reference output rb1/an5/v dac rb1 ttl cmos bi-directional i/o an5 an ? adc, comparator input v dac ? an dac output rb2/an6 rb2 ttl cmos bi-directional i/o an6 an ? adc, comparator input rb3/an7/opa rb3 ttl cmos bi-directional i/o an7 an ? adc, comparator input opa ? an opamp output rb4 rb4 ttl cmos bi-directional i/o rb5 rb5 ttl cmos bi-directional i/o rb6/c1/psmc1a rb6 ttl cmos bi-directional i/o c1 ? cmos comparator 1 output psmc1a ? cmos psmc output 1a
? 2001 microchip technology inc. preliminary ds41171a-page 9 pic16c781/782 rb7/c2/psmc1b/t1g rb7 ttl cmos bi-directional i/o c2 ? cmos comparator 2 output psmc1b ? cmos psmc output 1b t1g st ? timer 1 gate input av dd av dd power ? positive supply for analog av ss av ss power ? ground reference for analog v dd v dd power ? positive supply for logic and i/o pins v ss v ss power ? ground reference for logic and i/o pins legend: st = schmitt trigger an = analog od = open drain ttl = logic level xtal = crystal cmos = cmos output power = power supply table 1-1: pic16c781/782 pinout description (continued) name function input type output type description
pic16c781/782 ds41171a-page 10 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 11 pic16c781/782 2.0 memory organization there are two memory blocks in each of these picmicro ? microcontrollers. each block (program and data memory) has its own bus, so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16c781/782 devices have a 13-bit program counter capable of addressing an 8k x 14 program memory space. the pic16c781 has 1k x 14 words of program memory. the PIC16C782 has 2k x 14 words of program memory. accessing a location above the physically implemented address causes a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: pic16c781 program memory map and stack figure 2-2: PIC16C782 program memory map and stack 2.2 data memory organization the data memory is partitioned into multiple banks, which contain the general purpose registers and the special function registers. bits rp0 and rp1 are bank select bits. rp1 rp0 (status<6:5>) = 00 bank0 = 01 bank1 = 10 bank2 = 11 bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are the general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank are mirrored in another bank for code reduction and quicker access. pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 03ffh 0400h 1fffh pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 07ffh 0800h 1fffh
pic16c781/782 ds41171a-page 12 preliminary ? 2001 microchip technology inc. figure 2-3: register file map indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 tmr1l tmr1h t1con option_reg pcl status fsr trisa trisb pclath intcon pie1 pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as ? 0 ? . * not a physical register. indirect addr. (*) adres adcon0 general purpose register general purpose register efh f0h accesses 70h-7fh 96 bytes 32 bytes lvdcon file address file address refcon wpub iocb ansel bfh adcon1 tmr0 pcl status fsr portb pclath intcon pmdatl pmdath 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 120h 17fh bank 2 indirect addr. (*) 170h accesses 70h-7fh opacon file address cm2con1 cm1con0 cm2con0 pmadrh dacon0 option_reg pcl status fsr trisb pclath intcon pmcon1 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 1a0h 1ffh bank 3 indirect addr. (*) 1f0h accesses 70h-7fh file address pmadrl calcon psmccon0 psmccon1 dac
? 2001 microchip technology inc. preliminary ds41171a-page 13 pic16c781/782 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly, through the file select register (fsr). 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. table 2-1: pic16c781/782 special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: bank 0 00h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 23 01h tmr0 timer0 module ? s register xxxx xxxx 51 02h (2) pcl program counter's (pc) least significant byte 0000 0000 23 03h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 04h (2) fsr indirect data memory address pointer xxxx xxxx 23 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 26 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0000 35 07h ? unimplemented ? ? 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah (1, 2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23 0bh (2) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 19 0ch pir1 lvdif adif c2if c1if ? ? ? tmr1if 0000 ---0 21 0dh ? unimplemented ? ? 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx 55 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 55 10h t1con ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 57 11h ? unimplemented ? ? 12h ? unimplemented ? ? 13h ? unimplemented ? ? 14h ? unimplemented ? ? 15h ? unimplemented ? ? 16h ? unimplemented ? ? 17h ? unimplemented ? ? 18h ? unimplemented ? ? 19h ? unimplemented ? ? 1ah ? unimplemented ? ? 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adres adc result register xxxx xxxx 71 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 70 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are trans- ferred to the upper byte of the program counter. see section 2.9 for more detail. 2: these registers can be addressed from any bank.
pic16c781/782 ds41171a-page 14 preliminary ? 2001 microchip technology inc. bank 1 80h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 23 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 18 82h (2) pcl program counter ? s (pc) least significant byte 0000 0000 23 83h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 84h (2) fsr indirect data memory address pointer xxxx xxxx 23 85h trisa porta data direction register 1111 1111 26 86h trisb portb data direction register 1111 1111 35 87h ? unimplemented ? ? 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23 8bh (2) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 19 8ch pie1 lvdie adie c2ie c1ie ? ? ? tmr1ie 0000 ---0 20 8dh ? unimplemented ? ? 8eh pcon ? ? ? wdton oscf ? por bor ---q 1-qq 22, 120 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h ? unimplemented ? ? 93h ? unimplemented ? ? 94h ? unimplemented ? ? 95h wpub portb weak pull-up control 1111 1111 36 96h iocb portb interrupt-on-change control 1111 0000 36 97h ? unimplemented ? ? 98h ? unimplemented ? ? 99h ? unimplemented ? ? 9ah ? unimplemented ? ? 9bh refcon ? ? ? ? vren vroe ? ? ---- 00-- 61 9ch lvdcon ? ? bgst lvden lv3 lv2 lv1 lv0 --00 0101 66 9dh ansel analog channel select 1111 1111 25 9eh ? unimplemented ? ? 9fh adcon1 ? ? vcfg1 vcfg0 ? ? ? ? --00 ---- 71 table 2-1: pic16c781/782 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are trans- ferred to the upper byte of the program counter. see section 2.9 for more detail. 2: these registers can be addressed from any bank.
? 2001 microchip technology inc. preliminary ds41171a-page 15 pic16c781/782 bank 2 100h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 23 101h tmr0 timer0 module ? s register xxxx xxxx 51 102h (2) pcl program counter's (pc) least significant byte 0000 0000 23 103h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 104h (2) fsr indirect data memory address pointer xxxx xxxx 23 105h ? unimplemented ? ? 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0000 35 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23 10bh (2) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 19 10ch pmdatl pmd7 pmd6 pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 0000 0000 48 10dh pmadrl pma7 pma6 pma5 pma4 pma3 pma2 pma1 pma0 xxxx xxxx 48 10eh pmdath ? ? pmd13 pmd12 pmd11 pmd10 pmd9 pmd8 --00 0000 47 10fh pmadrh ? ? ? reserved reserved pma10 pma9 pma8 ---x xxxx 48 110h calcon cal calerr calref ? ? ? ? ? 000- ---- 85 111h psmccon0 smccl1 smccl0 mindc1 mindc0 maxdc1 maxdc0 dc1 dc0 0000 0000 104 112h psmccon1 smcon s1apol s1bpol ? scen smcom pwm/psm smccs 000- 0000 104 113h ? unimplemented ? ? 114h ? unimplemented ? ? 115h ? unimplemented ? ? 116h ? unimplemented ? ? 117h ? unimplemented ? ? 118h ? unimplemented ? ? 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 91 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 93 11bh cm2con1 mc1out mc2out ? ? ? ? ? c2sync 00-- ---0 94 11ch opacon opaon cmpen ? ? ? ? ? gbwp 00-- ---0 84 11dh ? unimplemented ? ? 11eh dac da7 da6 da5 da4 da3 da2 da1 da0 0000 0000 79 11fh dacon0 daon daoe ? ? ? ? dars1 dars0 00-- --00 79 table 2-1: pic16c781/782 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are trans- ferred to the upper byte of the program counter. see section 2.9 for more detail. 2: these registers can be addressed from any bank.
pic16c781/782 ds41171a-page 16 preliminary ? 2001 microchip technology inc. bank 3 180h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 23 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 18 182h ( 2) pcl program counter ? s (pc) least significant byte 0000 0000 23 183h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 184h (2) fsr indirect data memory address pointer xxxx xxxx 23 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 35 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23 18bh (2) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 19 18ch pmcon1 reserved ? ? ? ? ? ? rd 1--- ---0 47 18dh ? unimplemented ? ? 18eh ? unimplemented ? ? 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h ? unimplemented ? ? 192h ? unimplemented ? ? 193h ? unimplemented ? ? 194h ? unimplemented ? ? 195h ? unimplemented ? ? 196h ? unimplemented ? ? 197h ? unimplemented ? ? 198h ? unimplemented ? ? 199h ? unimplemented ? ? 19ah ? unimplemented ? ? 19bh ? unimplemented ? ? 19ch ? unimplemented ? ? 19dh ? unimplemented ? ? 19eh ? unimplemented ? ? 19fh ? unimplemented ? ? table 2-1: pic16c781/782 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are trans- ferred to the upper byte of the program counter. see section 2.9 for more detail. 2: these registers can be addressed from any bank.
? 2001 microchip technology inc. preliminary ds41171a-page 17 pic16c781/782 2.3 status register the status register, shown in register 2-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, or c bits, the write to these three bits is dis- abled. these bits are set or cleared according to the device logic. the to and pd bits are not writable. therefore, the result of an instruction with the status register as the destination may be different than intended. for example, clrf status clears the upper three bits and sets the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, since these instructions do not affect the z, c, or dc bits from the status register. for other instructions not affecting any status bits, see the "instruction set summary." register 2-1: status register (status: 03h, 83h, 103h, 183h) note: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit7 bit0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow, the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 18 preliminary ? 2001 microchip technology inc. 2.4 option_reg register the option_reg register is a readable and writable register which contains various control bits to configure: tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler) external int interrupt tmr0 weak pull-ups on portb register 2-2: option register (option_reg: 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit7 bit0 bit 7 rbpu : portb pull-up enable bit (1) 1 = portb weak pull-ups are disabled 0 = portb weak pull-ups are enabled by the wpub register bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits note 1: individual weak pull-ups on rb pins can be enabled/disabled from the weak pull-up portb register (wpub). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2001 microchip technology inc. preliminary ds41171a-page 19 pic16c781/782 2.5 intcon register the intcon register is a readable and writable regis- ter which contains: enable and interrupt flag bits for tmr0 register overflow enable and interrupt flag bits for the external interrupt (int) enable and interrupt flag bits for portb interrupt-on-change (iocb) peripheral interrupt enable bit global interrupt enable bit register 2-3: interrupt control register (intcon: 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t01e inte rbie t0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie: rb port change interrupt enable bit (1) 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit (1) 1 = when at least one of the rb7:rb0 pins changed state (must be cleared in software) 0 = none of the rb7:rb0 pins have changed state note 1: individual rb pin interrupt-on-change can be enabled/disabled from the interrupt- on-change portb register (iocb). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 20 preliminary ? 2001 microchip technology inc. 2.6 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. register 2-4: peripheral interrupt enable register (pie1: 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt (see register 2-3). r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 lvdie adie c2ie c1ie ? ? ? tmr1ie bit7 bit0 bit 7 lvdie: low voltage detect interrupt enable bit 1 = lvd interrupt is enabled 0 = lvd interrupt is disabled bit 6 adie: analog-to-digital converter interrupt enable bit 1 = enables the analog-to-digital converter interrupt 0 = disables the analog-to-digital converter interrupt bit 5 c2ie: comparator c2 interrupt enable bit 1 = enables the comparator c2 interrupt 0 = disables the comparator c2 interrupt bit 4 c1ie: comparator c1 interrupt enable bit 1 = enables the comparator c1 interrupt 0 = disables the comparator c1 interrupt bit 3-1 unimplemented: read as '0' bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 21 pic16c781/782 2.7 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 2-5: peripheral interrupt register (pir1 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 lvdif adif c2if c1if ? ? ? tmr1if bit7 bit 0 bit 7 lvdif: low voltage detect interrupt flag bit 1 = the supply voltage has fallen below the specified lvd voltage (must be cleared in software) 0 = the supply voltage is greater than the specified lvd voltage bit 6 adif: analog-to-digital converter interrupt flag bit 1 = an adc conversion completed (must be cleared in software) 0 = the adc conversion is not complete bit 5 c2if: comparator c2 interrupt flag bit 1 = comparator c2 input has crossed the threshold (must be cleared in software) 0 = comparator c2 input has not crossed the threshold bit 4 c1if: comparator c1 interrupt flag bit 1 = comparator c1 input has crossed the threshold (must be cleared in software) 0 = comparator c1 input has not crossed the threshold bit 3-1 unimplemented: read as ? 0 ? bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 22 preliminary ? 2001 microchip technology inc. 2.8 pcon register the power control (pcon) register contains two flag bits to allow determination of the source of the most recent reset: power-on reset (por ) external mclr reset power supply brown-out (bor ) reset the power control register also contains frequency select bits for the intrc oscillator and the wdt soft- ware enable bit. register 2-6: power control register (pcon: 8eh) note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the configuration word). direction of change typical time inactive minimum maximum 4 mhz 37 khz 100 s 300 s 37 khz 4 mhz 1.25 s 3.25 s note: when changing the internal oscillator speed (i.e., the oscf bit, intrc mode), the processor will be inactive during the oscillator frequency change. u-0 u-0 u-0 r/w-q r/w-1 u-0 r/w-q r/w-q ? ? ? wdton oscf ? por bor bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 wdton: wdt software enable bit if wdte bit (configuration word <3>) = 1: this bit is not writable, always reads ? 1 ? if wdte bit (configuration word <3>) = 0: 1 = wdt is enabled 0 = wdt is disabled bit 3 oscf: oscillator speed intrc mode bit 1 = 4 mhz typical 0 = 37 khz typical all other oscillator modes (x = ignored) bit 2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred legend: q = value depends on conditions r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 23 pic16c781/782 2.9 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register occur through the pclath register. 2.9.1 program memory paging pic16c781/782 devices are capable of addressing a continuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when performing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when performing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program mem- ory page is addressed. a return instruction pops a pc address off the stack onto the pc register. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). 2.10 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. mid-range devices have an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is poped in the event of a return, retlw, or a retfie instruction execution. pclath is not modified when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.11 indf the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is known as indirect addressing . reading indf itself, indirectly (fsr = 0), produces 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1. example 2-1: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-5. figure 2-4: loading of pc in different situations instruction with pcl as destination 8 alu 12 0 11 opcode <10:0> goto, call pclath<4:3> pclath pclath 87 pclath<4:0> 12 1110 8 7 0 pch pcl pch pcl 5 2
pic16c781/782 ds41171a-page 24 preliminary ? 2001 microchip technology inc. figure 2-5: direct/indirect addressing 2.12 effect of reset on core registers refer to table 2-2 for the effect of a reset operation on core registers. note 1: for register file map detail, see figure 2-3. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h table 2-2: effect of reset on core registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 02h pcl program counter ? s (pc) least significant byte 0000 0000 0000 0000 04h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 0ah pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0ch pir1 lvdif adif c2if c1if ? ? ? tmr1if 0000 ---0 0000 ---0 bank 1 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 xxxx xxxx 1111 1111 83h status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 lvdie adie c2ie c1ie ? ? ? tmr1ie 0000 ---0 0000 ---0 8eh pcon ? ? ? wdton oscf ? por bor ---q 1-qq ---q 1-qq legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: other (non power-up) resets include external reset through mclr and watchdog timer reset.
? 2001 microchip technology inc. preliminary ds41171a-page 25 pic16c781/782 3.0 i/o ports most pins for the i/o ports are multiplexed with an alter- nate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro ? mid-range reference manual (ds33023) 3.1 i/o port analog/digital mode the pic16c781/782 has two i/o ports: porta and portb. some of these port pins are mixed signal (can be digital or analog). when an analog signal is present on a pin, the pin must be configured as an analog input to prevent unnecessary current drawn from the power supply. the analog select register (ansel) allows the user to individually select the digital/analog mode on these pins. when the analog mode is active, the port pin always reads as a logic 0. register 3-1: analog select register (ansel: 9dh) note 1: on a power-on reset, the ansel regis- ter configures these mixed signal pins as analog mode: ra<3:0>, rb<3:0>. 2: if a pin is configured as analog mode, the pin always reads '0', even if the digital out- put is active. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 bit 7 bit 0 bit 7-0 ans<7:0>: select analog input function on an<7:0> bits 1 = analog input 0 = digital i/o note: setting a pin to an analog input disables the digital input buffer. the corresponding tris bit should be set to input mode when using pins as analog inputs. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 26 preliminary ? 2001 microchip technology inc. 3.2 porta and the trisa register porta is an 8-bit wide, bi-directional port with the exception of ra0, ra1 and ra5, which are inputs only. the corresponding data direction register is trisa. setting a trisa bit (= 1) makes the corresponding porta pin an input (i.e., disables the digital output). clearing a trisa bit (= 0) makes the corresponding porta pin an output (i.e., disables the digital output). reading the porta register reads the status of the pins, whereas writing to it, writes to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is then modified and written to the port data latch. pins ra<3:0> are multiplexed with analog functions: analog inputs an<3:0> to the a/d converter. v ref 1 and v ref 2 inputs to the comparators. opamp inverting/non-inverting inputs. pins ra<7:4> are multiplexed with digital functions: pin ra4 is multiplexed with the tmr0 module clock input. pin ra5 is multiplexed with the device reset (mclr ) and programming input (v pp ) function. pins ra6 and ra7 are multiplexed with the oscillator/clock i/o functions. ra6 can also be configured as the tmr1 clock input. porta has the following i/o characteristics: ra0, ra1, and ra5 are input only. ra4 is an open drain output. all other porta pins have full cmos buffer outputs. all porta pins have schmitt trigger inputs. example 3-1: initializing porta ;* this code block will configure porta ;* as follows ;* ra<7:4> digital outputs ;* ra<3:2> digital inputs ;* ra<1:0> analog inputs ;* rb<3:0> digital i/o ;* note 1: rb<3:0> configured as digital i/o ;* note 2: ra<7:6> availability depends on ;* the oscillator selection banksel porta ; select bank 0 clrf porta ; preset porta data ; reg banksel trisa ; select bank 1 movlw b?00001111?; digital i/o ; config data movwf trisa ; configure porta ; digital movlw b?00000011?; analog i/o config ; data movwf ansel ; configure porta ; analog 3.2.1 trisa, ansel, and control precedence the ansel and trisa registers are the primary soft- ware controls for the configuration of porta pins. trisa bits tri-state the output drivers of porta, and ansel register bits control the digital input buffers. it is important to program both registers when configuring a mixed signal port pin, as most peripherals cannot over- ride the trisa and ansel registers control. even if a peripheral has the ability to override control of the trisa and ansel registers, it is good programming practice to program both registers appropriately. there are specific cases in which the trisa and ansel registers can be overridden by a peripheral or a configuration bit, see figures 3-1 through 3-8 for details. note: when the analog peripherals are using any of these pins as analog input/output, the ansel register must have the proper value to individually select the analog mode of the corresponding pins. note: crystal (lp, xt and hs) oscillator configu- rations use pin ra6/osc2/clkout/ t1cki as osc2. in these modes, setting or clearing trisa<6> will have no effect and the pin will read as a zero (0).
? 2001 microchip technology inc. preliminary ds41171a-page 27 pic16c781/782 figure 3-1: block diagram of ra0/an0/opa+ pin qd en an0/opa+ (see figure 1-3) q d q ck ansel reg. wr ansel rd porta data bus data reg. v dd v ss analog function enable ra0/an0/opa+ ansel rd rd trisa ansel<0> trisa<0> function porta<0> read 0 x digital in pin 1 x analog in 0 v ss
pic16c781/782 ds41171a-page 28 preliminary ? 2001 microchip technology inc. figure 3-2: block diagram of ra1/an1/opa- pin q d en an1/opa- (see figure 1-3) q d q ck ansel reg. wr ansel rd porta data bus data reg. v dd v ss analog function enable ra1/an1/opa- rd ansel rd trisa ansel<1> trisa<1> function porta<1> read 0 x digital in pin 1 x analog in 0 v ss
? 2001 microchip technology inc. preliminary ds41171a-page 29 pic16c781/782 figure 3-3: block diagram of ra2/an2/v ref 2 pin an2/v ref 2 (see figure 1-3) data bus q d q ck q d q ck p n wr porta wr trisa data reg. tris reg. v ss v dd rd trisa q d q ck ansel reg. wr ansel rd porta v dd v ss q d en data reg. analog function enable rd ansel ra2/an2/ v ref 2 ansel<2> trisa<2> function porta<2> read 0 1 digital in pin 0 0 digital out pin 1 x analog in 0
pic16c781/782 ds41171a-page 30 preliminary ? 2001 microchip technology inc. figure 3-4: block diagram of ra3/an3/v ref 1 pin an3/v ref 1 (see figure 1-3) data bus q d q ck q d q ck p n wr porta wr trisa data reg. tris reg. v ss v dd rd trisa q d q ck ansel reg. wr ansel rd porta v dd v ss q d en data reg. analog function enable rd ansel ra3/an3/v ref 1 ansel<3> trisa<3> function porta<3> read 0 1 digital in pin 0 0 digital out pin 1 x analog in 0
? 2001 microchip technology inc. preliminary ds41171a-page 31 pic16c781/782 figure 3-5: block diagram of ra4/t0cki pin n trisa<4> porta<4> function porta<4> read 1 x digital in pin 0 0 0 output pin 0 1 hi-z output pin data reg. vss ra4/t0cki vss q q q q data reg. tris reg. d d ck ck data bus wr porta wr trisa rd trisa q d en rd porta tmr0 clock input
pic16c781/782 ds41171a-page 32 preliminary ? 2001 microchip technology inc. figure 3-6: block diagram of ra5/mclr /v pp pin data bus q d en rd porta rd trisa v ss to m c l r circuit mclr filter v ss program mode hv detect data reg. mclre ra5/mclr /v pp note 1: see configuration word <5>, register 14-1. mclre (1) trisa<5> function porta<5> read internal x digital in pin external x mclr 0
? 2001 microchip technology inc. preliminary ds41171a-page 33 pic16c781/782 figure 3-7: block diagram of ra6/osc2/clkout/t1cki pin data bus q d q ck p n wr porta wr trisa data reg. tris reg. rd trisa rd porta v ss v dd q d q ck oscillator circuit osc1 1 0 (intrc w/ clkout) or (rc w/ clkout) d q en (intrc w/ clkout) or (intrc) or (rc) data reg. (intrc w/o clkout) or clkout (f osc /4) ra6/osc2/clkout/t1cki t1cki n/a = not available w/ = with w/o = without note 1: see configuration word f osc <2:0>, register 14-1. osc mode (1) tmr1 oscillator pin function t1cki porta<6> read lp, xt, hs n/a osc2 n/a 0 rc, intrc w/ clkout n/a clkout n/a 0 intrc w/o clkout enabled osc2 (tmr1) n/a 0 intrc w/o clkout disabled digital i/o available pin rc w/o clkout n/a digital i/o available pin ec n/a digital i/o available pin (see table) (rc w/ clkout) (rc w/o clkout) or (ec) f osc <2:0> (1) t1oscen v dd v ss
pic16c781/782 ds41171a-page 34 preliminary ? 2001 microchip technology inc. figure 3-8: block diagram of ra7/osc1/clkin pin table 3-1: summary of registers associated with porta data bus q d q ck p n wr porta wr trisa data reg. tris reg. rd trisa rd porta v ss v dd q d q ck oscillator circuit osc2 (intrc w/o clkout) to chip clock drivers ec mode d q en data reg. ra7/osc1/clkin osc mode (1) tmr1 oscillator pin function porta<7> read lp, xt, hs n/a osc1 0 rc n/a osc1 0 ec n/a clkin 0 intrc enabled osc1 (tmr1) 0 intrc disabled digital i/o pin (intrc w/ clkout) or n/a = not available note 1: see configuration word f osc <2:0>, register 14-1. f osc <2:0> (1) t1oscen v dd v ss address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 uuuu 0000 85h trisa porta data direction register 1111 1111 1111 1111 9dh ansel an7 an6 an5 an4 an3 an2 an1 an0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? . shaded cells are not used by porta.
? 2001 microchip technology inc. preliminary ds41171a-page 35 pic16c781/782 3.3 portb and the trisb register portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1) makes the corresponding portb pin an input (i.e., puts the corresponding output driver into a hi-impedance mode). clearing a trisb bit (= 0) makes the corresponding portb pin an output (i.e., puts the contents of the output latch on the selected pin. example 3-2: initializing portb ;* this code block will configure port b ;* as follows ;* rb<7:6> analog inputs ;* rb<5:4> digital inputs ;* rb<3:2> digital inputs ;* rb<1:0> digital inputs ;* ra<3:0> digital i/o banksel portb ; select bank 0 clrf portb ; preset portb data ; reg. banksel trisb ; select bank 1 movlw b ? 11001111 ? ; digital i/o ; config data movwf trisb ; configure portb ; digital movlw b ? 00000011 ? ; analog i/o config ; data movwf ansel ; configure portb ; analog the rb0 pin can be configured as: digital i/o adc/comparator analog input (an4) external interrupt (int) voltage reference output (v r ) when the pin is used as an analog i/o, the ansel reg- ister must have bit 4 set to configure the rb0 pin as an analog input. pin rb1 is multiplexed with two analog functions: adc/ comparator analog input an5, and the output of the dac. when the pin is used as an analog i/o, the ansel register must have bit 5 set to configure the rb1 pin as an analog i/o. pin rb2 is multiplexed with the analog function adc/ comparator input an6. when the pin is used as an analog input, the ansel register must have bit 6 to select the analog mode for the pin. the rb3 pin is multiplexed with two analog functions: adc/comparator analog input an7, and the output of the opa module. when the pin is used as analog i/o, the ansel register must have bit 7 set to select the analog mode of the pin. pins rb<7:6> are multiplexed with the outputs of the two on-board comparators, the outputs of the psmc module, and the clock gate input for timer1. note, when enabled, these peripherals override the portb data register; however, trisb retains control of output drivers. therefore, trisb<7:6> must be programmed appropriately for comparator and psmc outputs to operate. 3.3.1 portb weak pull-up each of the portb pins has an internal weak pull-up resistance, which can be individually enabled from the wpub register. a single global enable bit, rbpu (option_reg<7>), can turn on/off all of the selected pull-ups. clearing the rbpu bit (option_reg<7>) enables the weak pull-up resistors (see register 3-2). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. 3.3.2 portb interrupt-on-change each of the portb pins, if configured as input, has the ability to generate an interrupt-on-change. to enable the interrupt-on-change feature, the corresponding bit must be set in the iocb register (see register 3-3). the rbie bit in the intcon register functions as a glo- bal enable bit to turn on/off the interrupt-on-change fea- ture. the selected inputs are compared to the old value latched on the last read of portb. the ? mismatch ? outputs are or-ed together to generate the rb port change interrupt with flag bit rbif (intcon<0>). the iocb interrupt can also awaken the device from sleep. the user, in the interrupt service routine, must clear the interrupt in the following manner: a) a read or write to portb. this copies the cur- rent state into the latch and ends the mismatch condition. b) clear flag bit rbif.
pic16c781/782 ds41171a-page 36 preliminary ? 2001 microchip technology inc. register 3-2: weak pull-up portb register (wpub: 95h) register 3-3: interrupt-on-change portb register (iocb: 96h) 3.3.3 trisb, ansel, and control precedence the ansel and trisb registers are the primary con- trols for the configuration of portb pins. trisb tri- states the output drivers of portb, and the ansel register disables the input buffers. it is important to pro- gram both registers when configuring a port pin, since most peripherals do not have precedence over the trisb and ansel registers ? control of the pin. even if a peripheral has the ability to override the control of the trisb and ansel registers, it is good practice to pro- gram both registers appropriately. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit7 bit0 bit 7-0 wpub<7:0>: portb weak pull-up control bits 1 = weak pull-up enabled for corresponding pin 0 = weak pull-up disabled for corresponding pin note 1: for the wpub register setting to take effect, the rbpu bit in the option_reg register must be cleared. 2: the weak pull-up device is automatically disabled if the pin is in output mode, i.e., (trisb = 0) for corresponding pin. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 iocb7 iocb6 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 bit7 bit0 bit 7-0 iocb<7:0>: interrupt-on-change portb control bits 1 = interrupt-on-change enabled for corresponding pin 0 = interrupt-on-change disabled for corresponding pin note 1: the interrupt enable bits, gie and rbie in the intcon register, must be set for indi- vidual interrupts to be recognized. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note 1: upon reset, the ansel register config- ures the rb<3:0> pins as analog inputs. 2: when programmed as analog inputs, rb<3:0> pins will read as ? 0 ? . 3: there are specific cases in which the functions of the trisb and ansel regis- ters can be overridden by a peripheral or configuration word (see figure 3-9 through figure 3-16 for details).
? 2001 microchip technology inc. preliminary ds41171a-page 37 pic16c781/782 figure 3-9: block diagram of rb0/int/an4/v r pin data bus wr portb wr trisb rd portb portb reg. tris reg. int input q d ck q d ck en qd en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q q d q ck ansel reg. wr ansel wr iocb q p v dd q an4/v r v r output vroe vren rb0/int/an4/v r rd wpub rd ansel analog function enable rd iocb vren & vroe ansel<4> trisb<0> function portb<0> read 0 0 1 digital in pin 0 0 0 digital out pin 0 1 x analog in 0 1 x x analog out 0 ttl v dd v ss
pic16c781/782 ds41171a-page 38 preliminary ? 2001 microchip technology inc. figure 3-10: block diagram of rb1/an5/v dac pin data bus wr portb wr trisb rd portb portb reg. tris reg. q d ck q d ck en q d en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q q d q ck ansel reg. wr ansel wr iocb q p v dd q an5/v dac v dac output daoe daon rb1/an5/v dac rd wpub rd ansel rd iocb analog function enable daon & daoe ansel<5> trisb<1> function portb<1> read 001digital inpin 0 0 0 digital out pin 0 1 x analog in 0 1 x x analog out 0 ttl v ss v dd
? 2001 microchip technology inc. preliminary ds41171a-page 39 pic16c781/782 figure 3-11: block diagram of rb2/an6 pin data bus wr portb wr trisb rd portb portb reg. tris reg. an6 q d ck q d ck en qd en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q q d q ck ansel reg. wr ansel wr iocb q p v dd q rb2/an6 rd wpub rd ansel rd iocb analog function enable ansel<6> trisb<2> function portb<2> read 0 1 digital in pin 0 0 digital out pin 1 x analog in 0 ttl v dd v ss
pic16c781/782 ds41171a-page 40 preliminary ? 2001 microchip technology inc. figure 3-12: block diagram of rb3/an7/opa pin analog hi-z = no internal drive on pin (analog input) during calibration. opa module ansel<7> adc/c1/c2 input function portb<3> read opaon cal_active 0 x 0 digital digital i/o pin 0 x 1 analog analog in 0 1 0 1 analog opa output 0 1 1 1 analog hi-z calibration 0 data bus wr portb wr trisb rd portb portb reg. tris reg. an7/opa q d ck q d ck en qd en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q q d q ck ansel reg. wr ansel wr iocb q p v dd q opaon opa output cal_active rb3/an7/opa rd wpub rd ansel rd iocb analog function enable ttl v dd v ss
? 2001 microchip technology inc. preliminary ds41171a-page 41 pic16c781/782 figure 3-13: block diagram of rb4 pin data bus wr portb wr trisb rd portb portb reg. tris reg. q d ck q d ck en qd en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q wr iocb q p v dd q rb4 rd wpub rd iocb trisb<4> function portb<4> read 0 digital out pin 1 digital in pin v dd v ss ttl
pic16c781/782 ds41171a-page 42 preliminary ? 2001 microchip technology inc. figure 3-14: block diagram of rb5 pin data bus wr portb wr trisb rd portb portb reg. tris reg. q d ck q d ck en q d en rd trisb rbpu weak pull-up p n v ss v dd q d ck q d ck wpub reg. iocb reg. wr wpub q d q en d q en q3 q1 ... set rbif from other rb<7:0> pins q wr iocb q p v dd q rb5 rd wpub rd iocb trisb<5> function portb<5> read 0 digital out pin 1 digital in pin ttl v dd v ss
? 2001 microchip technology inc. preliminary ds41171a-page 43 pic16c781/782 figure 3-15: block diagram of rb6/c1/psmc1a pin rd trisb p v ss n v dd rd portb wr portb wr trisb rbpu v dd weak pull-up p from other q d en set rbif rb<7:0> pins rd port q3 q1 serial programming clock ttl qd en v dd data bus q d ck wr wpub q iocb reg. wr iocb q d ck q d ck d ck q q q q c1oe smcon psmc1a c1out data reg. tris reg. rb6/c1/psmc1a rd wpub rd iocb psmc smcon comparator c1oe portb trisb<6> function x x 1 digital in 0 0 0 digital out 01 0 c1out 1x 0 psmc1a wpub reg. v ss
pic16c781/782 ds41171a-page 44 preliminary ? 2001 microchip technology inc. figure 3-16: block diagram of rb7/c2/psmc1b/t1g pin data reg. tris reg. rd trisb q d q ck q d q ck rd portb rbpu v dd weak pull-up p from other q d en q d en set rbif rb<7:0> pins rd port q3 q1 serial programming data v dd data bus q d ck wpub reg. wr wpub q q d ck iocb reg. wr iocb q smcon smcom scen c2oe sc switch psmc1b wr portb c2out wr trisb v dd p n v ss rd wpub rd iocb rb7/c2/psmc1b/t1g psmc module comparator c2oe portb trisb<7> function smcon smcom scen x x x x 1 digital in 0 x x 0 0 digital out 1 0 0 0 0 digital out 0xx1 0 c2out 1001 0 c2out 1 0 1 x 0 slope compensation 11xx 0 psmc1b ttl v ss and timer1 gate
? 2001 microchip technology inc. preliminary ds41171a-page 45 pic16c781/782 table 3-2: summary of registers associated with portb address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0000 uuuu 0000 86h trisb portb data direction register 1111 1111 1111 1111 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 95h wpub portb weak pull-up control 1111 1111 1111 1111 96h iocb portb interrupt-on-change control 1111 0000 1111 0000 9dh ansel an7 an6 an5 an4 an3 an2 an1 an0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? . shaded cells are not used by portb.
pic16c781/782 ds41171a-page 46 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 47 pic16c781/782 4.0 program memory read (pmr) program memory is readable during normal operation (full v dd range). it is read by indirect addressing through the following special function registers: pmcon1: control pmdath: data high pmdatl: data low pmadrh: address high pmadrl: address low when interfacing to the program memory block, the pmdath and pmdatl registers form a 2-byte word, which holds the 14-bit data. the pmadrh and pmadrl registers form a 2-byte word, which holds the 12-bit address of the program memory location being accessed. mid-range devices have up to 8k words of program eprom with an address range from 0h to 3fffh. when the device contains less memory than the full address range of the pmadrh:pmardl regis- ters, the most significant bits of the pmadrh register are ignored. 4.1 pmcon1 register pmcon1 is the control register for program memory accesses. control bit rd initiates a read operation. this bit cannot be cleared, only set, in software. it is cleared in hard- ware at completion of the read operation. 4.2 pmdath and pmdatl registers the pmdath:pmdatl registers are loaded with the contents of program memory addressed by the pmadrh and pmadrl registers upon completion of a program memory read command. register 4-1: program memory read control register 1 (pmcon1: 18ch) register 4-2: program memory data high (pmdath: 10eh) r-1 u-0 u-0 u-0 u-0 u-0 u-0 r/s-0 reserved ? ? ? ? ? ? rd bit7 bit0 bit 7 reserved: read as ? 1 ? bit 6-1 unimplemented: read as '0 bit 0 rd : read control bit 1 = initiates a program memory read (read takes 2 cycles, rd is cleared in hardware) 0 = reserved legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? pmd13 pmd12 pmd11 pmd10 pmd9 pmd8 bit7 bit0 bit 7-6 unimplemented: read as '0 bit 5-0 pmd<13:8>: program memory data bits the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 48 preliminary ? 2001 microchip technology inc. register 4-3: program memory data low (pmdatl: 10ch) register 4-4: program memory address high (pmadrh: 10fh) register 4-5: program memory address low (pmadrl: 10dh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmd7 pmd6 pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 bit7 bit0 bit 7-0 pmd<7:0>: program memory data bits the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? reserved reserved pma10 pma9 pma8 bit7 bit0 bit 7-5 unimplemented: read as '0' bit 4-3 reserved: read state is not guaranteed bit 2-0 pma<10:8> : pmr address bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pma7 pma6 pma5 pma4 pma3 pma2 pma1 pma0 bit7 bit0 bit 7-0 pma<7:0>: pmr address bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 49 pic16c781/782 4.3 reading the eprom program memory to read a program memory location, the user must write 2 bytes of the address to the pmadrh and pmadrl registers, then set control bit rd (pmcon1<0>). once the read control bit is set, the program memory read (pmr) controller uses the sec- ond instruction cycle after to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored . the data is available, in the very next cycle, in the pmdath and pmdatl registers. therefore, it can be read as 2 bytes in the following instructions. pmdath and pmdatl registers hold this value until another read or until reset. example 4-1: otp program memory read ;* this code block will read 1 word of program ;* memory at the memory address: ;* prog_addr_hi : prog_addr_lo ;* data will be returned in the variables; ;* prog_data_hi, prog_data_lo banksel pmadrl ; select bank 2 movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwf pmadrh ; store msb of address banksel pmcon1 ; select bank 3 clear gie bcf intcon, gie ; turn off ints bsf pmcon1,rd ; initiate read nop ; executed (fig 4-1) nop ; ignored (fig 4-1) bsf intcon, gie ; turn on ints movf pmdatl,w ; get lsb of word movwf prog_data_lo movf pmdath,w ; get msb of word movwf prog_data_hi note 1: interrupts must be disabled during the time from setting pmcon1<0> (rd) to the second instruction thereafter. 2: the following instructions should not be used following the start of a pmr read cycle: call, goto, btfss, btfsc, retfie, return, sleep.
pic16c781/782 ds41171a-page 50 preliminary ? 2001 microchip technology inc. 4.4 program memory read with code protect set when the device is code protected, the cpu can still perform the program memory read function. table 4-1: summary of registers associated with pmr figure 4-1: program memory read cycle execution address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 10ch pmdatl pmd7 pmd6 pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 0000 0000 0000 0000 10dh pmadrl pma7 pma6 pma5 pma4 pma3 pma2 pma1 pma0 xxxx xxxx uuuu uuuu 10eh pmdath ? ? pmd13 pmd12 pmd11 pmd10 pmd9 pmd8 --00 0000 --00 0000 10fh pmadrh ? ? ? reserved reserved pma10 pma9 pma8 ---x xxxx ---u uuuu 18ch pmcon1 reserved ? ? ? ? ? ? rd 1--- ---0 1--- ---0 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by pmr. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc+1) executed here forced nop executed here pc pc+1 pmadrh,pmadrl pc+3 pc+5 program rd bit pc+3 pc+4 instr(pc-1) executed here instr(pc+3) executed here instr(pc+4) executed here pmdath pmdatl register memory addr
? 2001 microchip technology inc. preliminary ds41171a-page 51 pic16c781/782 5.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable internal or external clock select edge select for external clock 8-bit software programmable prescaler interrupt on overflow from ffh to 00h figure 5-1 is a simplified block diagram of the timer0 module. additional information on timer modules is available in the picmicro ? mid-range reference manual, (ds33023). 5.1 timer0 operation timer0 can operate as either a timer or a counter. programming timer0 is via the option register (see register 2-2). timer0 mode is selected by clearing/setting the bit t0cs (option_reg<5>). in timer mode (t0cs = 0), the timer0 module increments every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 increments either on every rising, or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge, setting selects the falling edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal system clock. also, there is a delay in the actual incre- menting of timer0 after synchronization. additional information on external clock requirements is available in the picmicro ? mid-range reference manual, (ds33023). example 5-1: initializing timer0 ;* this code block will configure timer0 ;* for polling, internal clock & 1:16 ;* prescaler ;* ;* wait for tmr0 overflow code included banksel tmr0 ; select bank 0 clrf tmr0 ; clear timer0 ; register banksel option_reg ; select bank 1 movlw b ? 11000011 ? ; int on l2h movwf option_reg ; internal clk, ; pscaler 1:16 ******************************************** ;* wait for tmr0 overflow ;* t0_ovfl_wait tbfss intcon,t0if ; check for tmr0 ; overflow goto t0_ovfl_wait ; if clear, test ; again bcf intcon,t0if ; clear interrupt figure 5-1: timer0 block diagram note 1: t0cs, t0se, psa, ps<2:0> (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 5-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 t cy delay) psout data bus 8 psa ps<2:0> set interrupt flag bit t0if on overflow 3
pic16c781/782 ds41171a-page 52 preliminary ? 2001 microchip technology inc. 5.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 5-2). for simplicity, this counter is referred to as ? prescaler ? throughout this data sheet. the prescaler is not readable or writable. the psa and ps<2:0> bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa assigns the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa assigns the prescaler to the watchdog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0, movwf tmr0, bsf tmr0, x....etc .) will clear the prescaler. when assigned to wdt, a clrwdt instruc- tion clears the prescaler along with the wdt. 5.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ? on-the-fly ? during program execution. 5.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. 5.4 effects of reset a device reset will program timer0 for an external clock input on ra4/t0cki, hi-low edge, and no pres- caler. the tmr0 register is not cleared. note: there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assign- ment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. note: writing to tmr0 when the prescaler is assigned to timer0 clears the prescaler count, but does not change the prescaler assignment. note: to avoid an unintended device reset, a specific instruction sequence (shown in the picmicro ? mid-range reference man- ual, ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled.
? 2001 microchip technology inc. preliminary ds41171a-page 53 pic16c781/782 figure 5-2: block diagram of the timer0/wdt prescaler table 5-1: registers associated with timer0 ra4/t0cki t0se pin f osc /4 sync with tmr0 reg 8-bit prescaler 8 - to - 1 mux watchdog timer psa 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are (option_reg<5:0>). psa wdt enable bit 0 1 0 1 data bus set interrupt flag bit t0if on overflow 8 psa t0cs internal clocks (2 t cy delay) 0 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie adif t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? . shaded cells are not used by timer0.
pic16c781/782 ds41171a-page 54 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 55 pic16c781/782 6.0 timer1 module with gate control the timer1 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers:tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt on overflow from ffffh to 0000h external enable input (t1g pin with tmr1ge bit = 1) option for timer1 to use lp oscillator if device is configured to use intrc w/o clkout timer1 control register (t1con) is shown in register 6-1. figure 6-2 is a simplified block diagram of the timer1 module. 6.1 timer1 operation timer1 can operate in one of three modes: 1. 16-bit timer with prescaler. 2. 16-bit synchronous counter. 3. 16-bit asynchronous counter. in timer mode, timer1 is incremented on every instruc- tion cycle. in counter mode, timer1 is incremented on the rising edge of the external clock input t1cki (ra6/ osc2/clkout/t1cki). in addition, the counter mode clock can be synchronized to the microcontroller clock or run asynchronously. in counter and timer modes, the counter/timer clock can be gated by the t1g input. if an external clock oscillator is needed (and the micro- controller is using intrc w/o clkout), timer1 can use the lp oscillator as a clock source. example 6-1: timer1 initialization ;* this code block will configure timer1 for ;* polling, ext gate of int clk (fosc/4), & ;* 1:1 prescaler. ;* ;* wait for tmr1 overflow code included ;* banksel tmr1l ; select bank 0 clrf tmr1l ; clear tmr1 lsb clrf tmr1h ; clear tmr1 msb movlw b ? 01000000 ? ; gate, ps 1:1 movwf t1con ; int clk bsf t1con,tmr1on ; enable timer ;******************************************** ;* wait for tmr1 overflow t1_ovfl_wait banksel pir1 ; select bank 0 t1_wait ; tbfss pir1,tmr1if ; overflow? goto t1_wait ; if 0, again bcf pir1,tmr1if ; clear flag note 1: in counter mode, the counter increments on the rising edge of the clock.
pic16c781/782 ds41171a-page 56 preliminary ? 2001 microchip technology inc. 6.2 control register t1con control and configuration of timer1 is by means of the t1con register shown in register 6-1. timer1 is enabled by setting the tmr1on bit (t1con<0>). clearing tmr1on stops the timer, but does not clear the timer1 register. the tmr1cs bit (t1con<1>) determines the timer mode. when tmr1cs is set, the timer is configured as a counter and receives its clock from ra6/osc2/ clkout/t1cki. when cleared, the timer is configured as a timer and its clock is derived from f osc /4. the t1sync bit (t1con<2>) determines timer1 ? s syn- chronization. if cleared, the timer clock is synchronized to the system clock. if set, the timer is asynchronous. the timer1 clock gate function is enabled by setting the tmr1ge bit (t1con<6>). when tmr1ge is set, the t1g input will control the clock input to the timer/ counter. a low on the t1g input will cause timer1 to increment at the clock rate, a high will hold the timer at its present value. the t1oscen bit (t1con<3>) enables the lp oscil- lator as a clock source for timer1. this mode is a replacement for the regular external oscillator. t1ckps<1:0> determines the prescaler value for the timer. available prescaler values are: t1ckps<1:0> prescaler value bit 1 bit 0 11 1:8 10 1:4 01 1:2 00 1:1 note: to use the lp oscillator as the timer1 oscillator: 1. tmr1cs must be set. 2. t1oscen must be set. 3. the configuration word must select intrc w/o clkout.
? 2001 microchip technology inc. preliminary ds41171a-page 57 pic16c781/782 register 6-1: timer1 control register (t1con: address 10h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6 tmr1ge: timer1 gate enable bit if tmr1on = 0: this bit is ignored if tmr1on = 1: 1 = timer1 is on if t1g pin is low 0 = timer1 is on bit 5-4 t1ckps<1:0> : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen : lp oscillator enable control bit if intrc w/o clkout is selected in the configuration word, oscillator is active: 1 = lp oscillator is enabled for timer1 clock 0 = lp oscillator is off else: this bit is ignored bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs : timer1 clock source select bit 1 = external clock from pin ra6/osc2/clkout/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 58 preliminary ? 2001 microchip technology inc. figure 6-1: timer1 incrementing edge figure 6-2: timer1 on the pic16c781/782 block diagram t1cki = 1 when tmr1 t1cki = 0 when tmr1 1: arrows indicate counter increments. enabled enabled 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. note tmr1h tmr1l lp oscillator t1sync tmr1cs t1ckps<1:0> sleep input f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 ra7/osc1/clkin ra6/osc2/ set flag bit tmr1if on overflow tmr1 rb7/c2/ tmr1on tmr1ge tmr1on tmr1ge intrc t1oscen clkout/ to c2 comparator module tmr1 clock lpen w/o clkout mode t1cki psmc1b/t1g
? 2001 microchip technology inc. preliminary ds41171a-page 59 pic16c781/782 6.3 timer1 oscillator for the pic16c781/782 when the microcontroller is using intrc w/o clkout, timer1 can enable and use the lp oscillator as the timer1 oscillator. when enabled, timer1 oscillator operation is solely controlled by the t1oscen bit. the oscillator will operate independently of the tmr1on bit, allowing the programmer to start and stop the timer/counter using the tmr1on bit. the oscillator will also operate during sleep, allowing continuous timekeeping with timer1. the electrical requirements for the lp oscillator, when used as the timer1 oscilla- tor, are the same as when the oscillator is used in lp mode. 6.4 timer1 interrupt the tmr1 register pair (tmr1h and tmr1l) incre- ments from 0000h to ffffh and then rolls over to 0000h. when timer1 rolls over, the tmr1if bit (pir1<0>) is set. to enable an interrupt, the tmr1ie bit (pie1<0>), the gie (intcon<7>) and the peie bit (intcon<6>) must be set prior to rollover. to clear the interrupt, the tmr1if must be cleared by software prior to re-enabling interrupts. 6.5 effects of reset only por and bor resets clear t1con, disabling timer1. all other resets do not affect timer1. table 6-1: summary of registers associated with timer1 note: the oscillator requires a startup and stabi- lization time before use. therefore, t1oscen should be set, and a suitable delay observed, prior to enabling timer1 (see section 14.2). note: when enabling the timer1 interrupt, the user should clear both tmr1 registers and the tmr1if prior to enabling interrupts. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 lvdif adif c2if c1if ? ? ? tmrif 0000 ---0 0000 ---0 8ch pie1 lvdie adie c2ie c1ie ? ? ? tmrie 0000 ---0 0000 ---0 0eh tmr1l least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 -uuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by timer1.
pic16c781/782 ds41171a-page 60 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 61 pic16c781/782 7.0 voltage reference module (v r ) the voltage reference module provides an on-chip nominal 3.072v reference voltage for the following: adc converter dac converter vr output on the rb0/int/an4/vr pin the source for the reference voltage comes from a bandgap reference. the control register for this module is the refcon register shown in register 7-1. setting the vren flag (refcon<3>), enables the module. following initial start-up, the module should be allowed to stabilize for best accuracy. see section 17.0 for information concerning stabilization times and conditions. to route the reference voltage to the external rb0/int/ an4/v r pin, the vroe flag (refcon<2>) must be set. 7.1 effects of reset a device reset clears the refcon register, dis- abling the voltage reference. 7.2 registers associated with v r a summary of the registers associated with v r is shown in table 7-1. register 7-1: voltage reference control register (refcon: 9bh) table 7-1: summary of registers associated with v r note 1: if the v r module is to be used by the dac, adc, or v r output:, the v r module must be enabled using vren (refcon<3>). 2: when vren = 1 and vroe = 1, the out- put driver for rb0/int/an4/v r will be driven tri-state and the analog driver for the v r output will be enabled. a read of rb0 will return a ? 0 ? . u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 ? ? ? ? vren vroe ? ? bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 vren: voltage reference enable bit (v r = 3.072v nominal) 1 = v r reference is enabled 0 = v r reference is disabled bit 2 vroe: voltage reference output enable bit if vren = 1: 1 = enabled, v r voltage reference is output on rb0 0 = voltage reference is not available externally if vren = 0: this bit is ignored bit 1-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09bh refcon ? ? ? ? vren vroe ? ? ---- 00-- ---- 00--
pic16c781/782 ds41171a-page 62 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 63 pic16c781/782 8.0 programmable low voltage detect module (plvd) the plvd module monitors the v dd power supply of the microcontroller and signals the microcontroller whenever v dd drops below its trip voltage. the signal acts as an ? early warning ? of power-down, allowing the microcontroller to finish any critical ? housekeeping ? tasks prior to completing power-down. figure 8-1 demonstrates a potential application of the plvd module (typical battery operation). at time t a , the v dd supply voltage (v a ) has fallen below the plvd ref- erence voltage. the plvd voltage comparator then sets the lvdif bit (pir<7>), indicating a low voltage condition. the time between t a and t b is then available to the microcontroller for completing a ? graceful ? power- down before v dd falls below v b . figure 8-2 is a simplified block diagram for the plvd module, showing the v dd resistor ladder, control regis- ter, and voltage comparator. figure 8-1: typical low voltage detect application 8.1 control register the plvd module is controlled via the lvdcon regis- ter shown in register 8-1. to enable the module for testing, the lvden bit (lvdcon<4>) must be set. this will enable the on- board voltage reference and connect the resistor lad- der between v dd and vss. clearing lvden will disable the module and disconnect the resistor ladder from vss. the trip voltage is set by programming the lvdl<3:0> bit (lvdcon<3.0>). the voltages available are listed in register 8-1. note that voltages below 2.5v and above 4.75v are not available and should not be used. the bgst bit (lvdcon<5>) is a status bit indicating that the internal reference voltage bandgap has stabi- lized. no test should be performed until this bit is set. the low voltage output flag for the plvd module is the lvdif bit (pir1<6>). note: for low power applications, current drain can be minimized by enabling the module only during regular polled testing. when not in use, the module is disabled by clear- ing the lvden bit (lvdcon<4>), which also powers down the resistor ladder between v dd and vss. time voltage v a v b t a t b v a = plvd trip point v b = minimum valid device operating voltage legend:
pic16c781/782 ds41171a-page 64 preliminary ? 2001 microchip technology inc. 8.2 operation the plvd indicates a low voltage condition by setting the lvdif bit in the pir1 register. once set by the plvd module, the lvdif bit will remain set until cleared by software. for proper indication of a low volt- age condition, the user should clear this bit prior to testing. to test for a low voltage condition, the plvd module compares the divided output of v dd against an internal bandgap reference. the plvd module automatically enables this reference whenever it is enabled and pro- vides a stability bit, bgst, to indicate when it has sta- bilized. the bandgap reference is also enabled by other modules within the pic16c781/782 as part of their operation. other modules using the bandgap include the following: v r module bor module opa calibration module figure 8-2: low voltage detect block diagram lvdif v dd 16 to 1 mux lvden plvd control register internally generated reference voltage
? 2001 microchip technology inc. preliminary ds41171a-page 65 pic16c781/782 if another module has enabled the bandgap, then the reference will be stable when the plvd module is enabled and the bgst flag can be ignored. however, if the bandgap has not been previously enabled, the lvdif bit will not be valid until the bgst bit is set (see figure 8-3). systems using the plvd interrupt should not enable the interrupt until after the reference is sta- ble to prevent spurious interrupts. 8.2.1 setting up the plvd module the following steps are needed to set up the plvd module: 1. write the value to the lv3:lv0 bits (lvdcon register), which selects the desired plvd trip point. 2. ensure that plvd interrupts are disabled (the lvdie bit is cleared, or the gie bit is cleared). 3. enable the plvd module (set the lvden bit in the lvdcon register). 4. wait for the plvd module to stabilize (the bgst bit to become set). 5. clear the plvd interrupt flag, which may have falsely become set until the plvd module has stabilized (clear the lvdif bit). 6. enable the plvd interrupt (set the lvdie and the gie bits). figure 8-3: low voltage detect waveforms . vlvd v dd lvdif vlvd v dd enable lvd internally generated lvdif may not be set enable lvd lvdif lvdif cleared in software lvdif cleared in software case 1: case 2: reference stable internally generated reference stable attempt to clear lvdif in software but remains set as lvd condition still exists
pic16c781/782 ds41171a-page 66 preliminary ? 2001 microchip technology inc. register 8-1: programmable low voltage detect register (lvdcon: 9ch) u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? bgst lvden lv3 lv2 lv1 lv0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5 bgst: internal reference voltage stable flag bit 1 = reference is stable 0 = reference is not stable bit 4 lvden: low voltage detect power enable bit 1 = enables plvd, powers up lvd circuit 0 = disables plvd, powers down lvd circuit. bit 3-0 lv<3:0>: low voltage detection limit bits 1111 = reserved 1110 = 4.5v typical 1101 = 4.2v typical 1100 = 4.0v typical 1011 = 3.8v typical 1010 = 3.6v typical 1001 = 3.5v typical 1000 = 3.3v typical 0111 = 3.0v typical 0110 = 2.8v typical 0101 = 2.7v typical 0100 = 2.5v typical 0011 = below valid operating voltage 0010 = below valid operating voltage 0001 = below valid operating voltage 0000 = below valid operating voltage legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 67 pic16c781/782 example 8-1 shows the configuration of the plvd mod- ule and a sample polling routine to monitor for low volt- age conditions. example 8-1: plvd example ;************************************************ ;* this code block will configure the plvd for polling ;* and set the trip point for 4.2 to 4.4 volts ;* includes polling routine ;* banksel lvdcon ; select bank 1 bcf pie1,lvdie ; disable plvd interrupt movlw b ? 00011101 ? movwf lvdcon ; enable plvd, 4.2-4.4v trip wrm_up btfss lvdcon,bgst ; goto wrm_up ; banksel pir1 ; select bank 0 bcf pir1,lvdif ; clear plvd interrupt flag ;************************************************** ;* test for plvd trip banksel pir1 ; select bank 0 btfsc pir1,lvdif ; test for plvd trip goto lo_v_det ; if tripped save 4 pwrfail 8.3 operation during sleep when enabled, the plvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit is set and the device awakens from sleep. device execution continues from the interrupt vector address, if interrupts have been globally enabled. 8.4 effects of a reset a device reset forces all registers to their reset state. this forces the plvd module to be disabled. 8.5 low voltage detect registers the registers associated with programmable low volt- age detect are shown in table 8-1. table 8-1: summary of registers associated with low voltage detect address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09ch lvdcon ? ? bgst lvden lv3 lv2 lv1 lv0 --00 0101 --00 0101 08ch pie1 lvdie adie c2ie c2ie ? ? ? tmr1ie 0000 ---0 0000 ---0 08ch pir1 lvdif adif c2if c2if ? ? ? tmr1if 0000 ---0 0000 ---0
pic16c781/782 ds41171a-page 68 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 69 pic16c781/782 9.0 analog-to-digital converter (adc) module the 8-bit adc module, shown in figure 9-1, has 10 inputs in the pic16c781/782: 8 external channels, an<7:0> (ra<3:0> and rb<3:0>) 2 internal channels, v r and v dac the adc allows conversion of an analog input signal to a corresponding 8-bit digital value. the desired chan- nel is connected to a sample-and-hold by the input multiplexers. the output of the sample-and-hold cap- tures a snapshot of the voltage and holds it for the adc. the adc then generates the 8-bit result via suc- cessive approximation. the analog reference voltage (adc ref ) is software selectable from the following options: the analog positive supply: av dd the reference input for comparator c1: v ref 1 the voltage reference module output: v r the dac converter module output: v dac the adc has the unique feature of being able to oper- ate while the device is in sleep mode. to operate in sleep, the adc conversion clock must be derived from the adc ? s dedicated internal rc oscillator. figure 9-1: adc module block diagram ra0/an0/opa+ ra1/an1/opa- ra2/an2/v ref 2 rb0/int/an4/v r rb1/an5/v dac rb2/an6 rb3/an7/opa ra3/an3/v ref 1 0 1 2 3 4 5 6 7 0 1 2 av dd v ref 1 v r adc ref adc 3 v dac vcfg<1:0> adon go/done adres 8 8 9 sample and hold voltage comparator module opa module 4 dac module v r module chs<3:0>
pic16c781/782 ds41171a-page 70 preliminary ? 2001 microchip technology inc. 9.1 control registers the adc module has three registers. these registers are: adc result register: adres adc control register 0: adcon0 adc control register 1: adcon1 the adcon0 register, shown in register 9-1, controls the operations and input channel selection for the adc module. the adcon1 register, shown in register 9-3, selects the voltage reference used by the adc module. the adres register, shown in register 9-2, holds the 8-bit result of the conversion. additional information on using the adc module can be found in the picmicro ? mid-range mcu family ref- erence manual (ds33023) and in application note an546 (ds00546). 9.1.1 adcon0 register the adcon0 register, shown in register 9-1, controls the following: clock source and prescaler input channel conversion start/stop enabling of the adc module setting the adon bit, adcon0<0>, enables the adc module. clearing adon disables the module and ter- minates any conversion in process. the adcs<1:0> bits (adcon0<7:6>) determine the clock source used by the adc module. the chs<3:0> bits (adcon0<5:3,1>) determine the input channel to the adc module. chs<3> specifically determines whether the source is internal or external. setting the go/done bit (adcon0<2>) initiates the conversion process. the adc clears this bit at the completion of the conversion process. register 9-1: adc control register 0 (adcon0: 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/s-0 r/w-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon bit 7 bit 0 bit 7-6 adcs<1:0>: adc conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = adrc (clock derived from a dedicated rc oscillator) bit 5-3 chs<2:0>: analog channel select bits (select which channel to convert) if chs3 = 0: if chs3 = 1: 000 = channel 0 (an0) 000 = v r 001 = channel 1 (an1) 001 = v dac 010 = channel 2 (an2) 010 = reserved. do not use. 011 = channel 3 (an3) 011 = reserved. do not use. 100 = channel 4 (an4) 100 = reserved. do not use. 101 = channel 5 (an5) 101 = reserved. do not use. 110 = channel 6 (an6) 110 = reserved. do not use. 111 = channel 7 (an7) 111 = reserved. do not use. bit 2 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. 0 = adc conversion is not in progress (this bit is cleared by hardware when conversion is complete) bit 1 chs3: analog channel select bit 1 = internal channel selected for conversion 0 = external channel selected for conversion bit 0 adon: adc on bit 1 = adc enabled 0 = adc disabled legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 71 pic16c781/782 9.1.2 adcon1 register the adcon1 register, shown in register 9-3, controls the reference voltage selection for the adc module. bits vcfg<1:0> select the reference voltage (adc ref ). 9.1.3 adres register the adres register, shown in register 9-2, contains the 8-bit result of the conversion. at the completion of the adc conversion: 8-bit result is loaded into adres. go/done bit (adocn0<2>) is cleared. adc interrupt flag bit adif (intcon<6> and pir1<6>) are set. if the adc interrupt is enabled, an interrupt is also generated. register 9-2: adc result register (adres: 1eh) register 9-3: adc control register 1 (adcon1: 9fh) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 bit 7 bit 0 bit 7-0 ad<7:0>: adc conversion results bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ? vcfg1 vcfg0 ? ? ? ? bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 vcfg<1:0>: voltage reference configuration bits 00 = av dd 01 = v ref 1 10 = v r 11 = v dac bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 72 preliminary ? 2001 microchip technology inc. 9.2 configuring the adc module 9.2.1 configuring analog port pins the ansel and trisb registers control the operation of the adc port pins. the port pins to be used as ana- log inputs must have their corresponding trisb bits set (= 1). the proper ansel bits must also be set (ana- log input) to disable the digital input buffer. 9.2.2 configuring the reference voltages the vcfg<5:4> bits in the adcon1 register configure the adc module reference voltage input, adc ref . the reference input can come from any of the following: internal voltage reference (v r ) external comparator c1 reference (v ref 1) dac output (v dac ) analog positive supply (a vdd ) if an external reference is chosen for the adc ref input, the port pin that multiplexes with the incoming external reference must also be configured as an analog input. 9.2.3 selecting the adc conversion clock the adc conversion cycle requires 9.5t ad . the source of the adc conversion clock is software selectable. the four possible options for adc clock are: f osc /2 f osc /8 f osc /32 adrc (clock derived from a dedicated internal rc oscillator) for correct adc conversion, the adc conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 sec. table 9-1 shows the resultant t ad times derived from the device operating frequencies and the adc clock source selected. table 9-1: tad vs . device operating frequencies: pic16c781/782 legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when device frequency is greater than 1 mhz, the rc adc conversion clock source is recommended for sleep operation only. note 1: the adc operation is independent of the state of the trisb or ansel bits. these bits must be configured by the firmware prior to initiation of an adc conversion. 2: when reading the porta or portb reg- isters, all pins configured as analog input channels will read as a ? 0 ? . 3: analog levels on any pin that is defined as a digital input, including an<7:0>, may cause the input buffer to consume excess supply current. adc clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33khz 2 t osc 00 100 ns (2 ) 400 ns (2) 1.6 s 6 s 8 t osc 01 400 ns 1.6 s6.4 s 24 s (3) 32 t osc 10 1.6 s6.4 s25.6 s (3) 96 s (3) rc 11 2 - 6 s (1,4) 2 - 6 s (1,4) 2 - 6 s (1,4) 2 - 6 s (1)
? 2001 microchip technology inc. preliminary ds41171a-page 73 pic16c781/782 9.2.4 initiating a conversion the analog-to-digital conversion is initiated by setting the go/done bit in adcon0 register. when the con- version is complete, the adc module: clears the go/done bit sets the adif flag in the pir1 register generates an interrupt if the adie, peie, and gie bits are set. if the conversion must be aborted, the go/done bit can be cleared in software. the adres register will not be updated with the partially completed adc conver- sion sample. instead, the adres will contain the value from the last completed conversion. after an aborted conversion, a 2t ad delay is required before another acquisition/conversion can be initiated. following the delay, an input acquisition is automatically started on the selected channel. 9.3 adc acquisition requirements for the adc module to meet its specified accuracy, the internal sample-and-hold capacitor (c hold ) must be allowed to charge to within ? lsb of the voltage present on the input channel (see analog input model in figure 9-2). the analog source resistance (r s ) and the internal sampling switch resistance (r ss ) will directly affect the time required to charge c hold . in addition, r ss will vary over the power supply voltage range (av dd ), and r s will affect the input offset voltage at the analog input (due to pin leakage current). therefore: 1. the maximum recommended impedance for any analog sources is 10 kohms. 2. following any change in the analog input chan- nel selection, a minimum acquisition delay must be observed before another conversion can begin (see equation 9-1). to calculate the minimum acquisition time, equation 9-1 may be used. this equation calculates the acquisition time to within ? lsb error, assuming an 8-bit conver- sion (512 steps for the pic16c781/782 adc). the ? lsb error is the maximum error allowed for the adc to meet its specified accuracy. equation 9-1: adc minimum charging time example 9-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following system assumptions. c hold = 51.2 pf r s = 10k ? 1/2 lsb error r ss = 7k ? @ v dd = 5v example 9-1: calculating the minimum required acquisition time note: the go/done bit should not be set in the same instruction that turns on the adc. v hold = (adc ref -(adc ref /512))?(1-e -t cap /c hold (r ic +rss+rs) ) given: v hold = (adc ref /512), for 1/2lsb resolution the above equation reduces to: t cap = -(51.2 pf)(1 k ? + r ss + r s ) ln(1/511) note 1: the reference voltage (adc ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ?. this is required to meet the pin leakage specifi- cation. 4: after a conversion has completed, a 1.0t ad delay must be completed before acquisition can begin again. during this time the holding capacitor is not connected to the selected adc input channel. t acq = amplifier setting time + holding capacitor charging time + temperature coefficien t t acq =5 s + t cap + [(temp - 25 c)(0.05 s/ c)] t cap =-c hold (r ic + r ss + r s ) in(1/511) -51.2 pf (1 k ? + 7 k ? + 10 k ?) in(0.0020) -51.2 pf (18 k ? ) in(0.0020) -0.921 s (-6.2364) 5.747 s t acq =5 s + 5.747 s + [(50 c -25 c)(0.05 s/ c)] 10.747 s + 1.25 s 11.997 s
pic16c781/782 ds41171a-page 74 preliminary ? 2001 microchip technology inc. figure 9-2: analog input model 9.4 adc configuration and conversion example 9-2 demonstrates an adc conversion. the ra0/an0 pin is configured as the analog input. the ref- erence voltage selected is the device av dd . the adc interrupt is enabled, and the adc conversion clock is adrc. clearing the go/done bit during a conversion aborts the current conversion. the adres register is not updated with the partially completed adc conversion sample. that is, the adres register continues to con- tain the value of the last completed conversion (or the last value written to the adres register). after the adc conversion is aborted, a 2t ad wait period is required before the next acquisition is started. after this 2t ad wait period, an acquisition is automatically started on the selected channel. example 9-2: adc conversion ;******************************************** ;* this code block will configure the adc ;* for polling, avdd as reference, rc clock ;* and ra0 input. ;* ;* conversion start & wait for complete ;* polling code included. ;* banksel adcon1 ; select bank 1 clrf adcon1 ; avdd as vref bsf trisa,0 ; set ra0 as input bsf ansel,0 ; set ra0 as analog banksel adcon0 ; select bank0 movlw b ? 11000001 ? movwf adcon0 ; rc, ch 0, adc on ;******************************************** ;* start & wait for adc complete, assumes ;* minimum acquisition delay from ;* configuration. adc_cnvrt banksel adcon0 ; select bank 0 bsf adcon0,go ; start convert adc_cn_loop btfsc adcon0,go ; test for end goto adc_cn_loop ; if not, wait movf adres,w ; get result cpin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k ? ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 2001 microchip technology inc. preliminary ds41171a-page 75 pic16c781/782 9.4.1 faster conversion/lower resolution trade-off not all applications require a result having 8-bits of res- olution. some may instead, require a faster conversion time. the adc module allows users to make a trade-off of conversion speed for resolution. regardless of the resolution required, the acquisition time is the same. to speed up the conversion, the clock source of the adc module may be switched during the conversion, so that the t ad time violates the minimum specified time (see the applicable electrical specification). once the switch is made, all the following adc result bits are invalid (see adc conversion timing in the electrical specifi- cations section). the clock source may only be switched between the three oscillator options (it cannot be switched from/to rc). the equation to determine the time before the oscillator must be switched for a desired resolution is as follows: conversion time = 2t ad + n t ad + (8 - n)(2t osc ) where: n = number of bits of resolution required. since the t ad is based on the device oscillator, the user must employ some method (such as a timer, software loop, etc.) to determine when the adc oscillator must be changed. 9.5 adc operation during sleep the adc module can operate during sleep mode. this requires that the adc clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the adc module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed the go/done bit is cleared, and the result is loaded into the adres register. if the adc interrupt is enabled, the device awakens from sleep. if the adc interrupt is not enabled, the adc module is turned off, although the adon bit remains set. when the adc clock source is another clock option (not rc), a sleep instruction causes the present con- version to be aborted and the adc module to be turned off. the adon bit remains set. turning off the adc places the adc module in its low- est current consumption state. 9.6 adc accuracy/error the absolute accuracy (absolute error) specified for the adc converter includes the sum of all contributions for: offset error gain error quantization error integral non-linearity error differential non-linearity error monotonicity the absolute error is defined as the maximum devia- tion from an actual transition versus an ideal transition for any code. the absolute error of the adc converter is specified as < 1 lsb for adc ref = v dd (over the device ? s specified operating range). however, the accuracy of the adc converter degrades as v dd diverges from v ref . for a given range of analog inputs, the output digital code will be the same. this is due to the quantization of the analog input to a digital code. quantization error is typically 1/2 lsb and is inherent in the analog to digital conversion process. the only way to reduce quantization error is to use an adc with greater resolu- tion of the adc converter. offset error measures the first actual transition of a code versus the first ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system, or introduced into a sys- tem, through the interaction of the total leakage current and source impedance at the analog input. gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference in gain error to full scale error is that full scale does not take offset error into account. gain error can be cali- brated out in software. linearity error refers to the uniformity of the code changes. linearity errors cannot be calibrated out of the system. integral non-linearity error measures the actual code transition versus the ideal code transition, adjusted by the gain error for each code. differential non-linearity measures the maximum actual code width versus the ideal code width. this measure is unadjusted. if the linearity errors are very large, the adc may become non-monotonic . this occurs when the digital values for one or more input voltages are less than the value for a lower input voltage. note: for the adc module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an adc conversion in sleep, ensure the sleep instruction immediately follows the instruc- tion that sets the go/done bit.
pic16c781/782 ds41171a-page 76 preliminary ? 2001 microchip technology inc. 9.6.1 clock noise in systems where the device frequency is low, use of the adc rc clock is preferred. at moderate to high fre- quencies, t ad should be derived from the device oscil- lator. t ad must not violate the minimum and should be 8 s for preferred operation. this is because t ad , when derived from t osc , is kept away from on-chip phase clock transitions. this reduces, to a large extent, the effects of digital switching noise. this is not possi- ble with the rc derived clock. the loss of accuracy due to digital switching noise can be significant if many i/o pins are active. in systems where the device enters sleep mode after the start of the adc conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep is stopped. this method gives high accuracy. 9.7 effects of a reset a device reset forces all registers to their reset state. this forces the adc module to be turned off, and any conversion is aborted. the value that is in the adres register is not modified for a power-on reset. the adres register contains unknown data after a power-on reset. 9.8 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.2v, then the accuracy of the conver- sion is out of specification. an external rc filter is sometimes added for anti- aliasing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k ? recommended specification. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 9.9 transfer function the ideal transfer function of the adc converter is as follows: the first transition occurs when the analog input voltage (v ain ) is analog adc ref /256 (figure 9-3). 9.10 references a good reference for adc converters is the " analog- digital conversion handbook " third edition, published by prentice hall (isbn 0-13-03-2848-0). figure 9-3: adc transfer function note: care must be taken when using the rb2/ an6 pin in adc conversions due to its proximity to the osc1 pin. digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb ( full scale) analog input voltage
? 2001 microchip technology inc. preliminary ds41171a-page 77 pic16c781/782 figure 9-4: flow chart of adc operation table 9-2: registers/bits associated with adc, pic16c781/782 acquire adon = 0 adon = 0? go = 0? adc clock go = 0 adif = 0 abort conversion sleep power-down a/d wait 2t ad wake-up ye s no ye s no no ye s finish conversion go = 0 adif = 1 device in no ye s finish conversion go = 0 adif = 1 wait 2t ad stay in sleep selected channel = rc? no yes start of adc conversion delayed 1 instruction cycle from power-down adc ye s no wait 2t ad finish conversion go = 0 adif = 1 sleep? sleep instruction ? sleep? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 lvdie adie c2ie c1ie ? ? ? tmr1ie 0000 ---0 0000 ---0 0ch pir1 lvdif adif c2if c1if ? ? ? tmr1if 0000 ---0 0000 ---0 1eh adres adc result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 9fh adcon1 ? ? vcfg1 vcfg0 ? ? ? ? --00 ---- --00 ---- 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 uuuu 0000 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0000 uuuu 0000 9dh ansel analog channel select 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for adc conversion.
pic16c781/782 ds41171a-page 78 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 79 pic16c781/782 10.0 digital-to-analog converter (dac) module the digital-to-analog converter (dac) module gener- ates an output voltage proportional to the value in the 8-bit dac register (see figure 10-1). the output of the dac module can be configured to drive: the reference input to the adc module the reference input to comparators c1 and c2 an analog output on pin rb1/an5/v dac the voltage reference input to the dac can be selected from: analog supply av dd comparator c1 v ref 1 voltage reference v r 10.1 control registers the dac module is controlled via two special function registers: dacon0 and dac. the dacon0 register, shown in register 10-1: enables dac enables output on rb1/an5/v dac selects reference voltage the dac register, shown in register 10-2, sets the out- put of the dac. register 10-1: digital-to-analog converter control register0 (dacon0: 11fh) register 10-2: digital-to-analog converter register (dac: 11eh) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 daon daoe ? ? ? ? dars1 dars0 bit 7 bit 0 bit 7 daon: digital-to-analog converter enable bit 1 = dac enabled 0 = dac disabled bit 6 daoe: digital-to-analog converter output enable bit 1 = output on the v dac pin 0 = output is not available for external use bit 5-2 unimplemented: read as ? 0 ? bit 1-0 dars<1:0>: digital-to-analog converter voltage reference select bits, dac ref 00 = analog supply, av dd 01 = comparator reference, v ref 1 pin 10 = voltage reference, v r 11 = reserved, do not use legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 da7 da6 da5 da4 da3 da2 da1 da0 bit 7 bit 0 bit 7-0 da<7:0>: digital-to-analog converter digital input bits legend: r = readable bit w = writable bit - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared
pic16c781/782 ds41171a-page 80 preliminary ? 2001 microchip technology inc. 10.2 control register the dac module is enabled by setting the daon bit (dacon0<7>). bits dars<1:0> (dacon0<1:0>) determine the volt- age reference for the dac module. to output the dac voltage, the daoe bit (dacon0<6>) and daon must be set. to use the dac output internally, the appropriate reference select bits in the destination module must be set. figure 10-1: dac converter block diagram note 1: to enable the dac output as a reference for the adc module, vcfg<1:0> in adcon1 must be set. 2: to enable the dac output as a reference for the comparator module, c1r/c2r bits (cm1con0<2>/cm2con0<2>) must be set. dars<1:0> av dd 0 1 2 3 dac converter daoe & daon v ref 1 v r n/c daon dac register 8 v dac pin v dac voltage for adc and comparators dac ref en reference
? 2001 microchip technology inc. preliminary ds41171a-page 81 pic16c781/782 10.3 dac configuration example 10-1 shows a sample configuration for the dac module. the port pin is configured, av dd is selected for the voltage reference, and the dac output is enabled. example 10-1: dac configuration ;* this code block will configure the dac ;* for avdd voltage ref, and rb1/an5/vdac as ;* output. banksel trisb ; select bank 1 bsf trisb,1 ; set rb1 input bsf ansel,1 ; set rb1 as analog banksel dacon0 ; select bank 2 clrf dac ; dac to 00 movlw b ? 11000000 ? ; enable dac output movwf dacon0 ; set ref = vdd movlw dac_value movwf dac ; set dac output 10.4 effects of reset a device reset forces all registers to their reset state. this forces the following conditions: dac module is off reference input to av dd output disabled dac register is cleared 10.5 dac module accuracy/error the accuracy/error specified for the dac includes: integral non-linearity error differential non-linearity error gain error offset error monotonicity figure 10-2: dac transfer function offset error measures the first actual transition of a code versus the first ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system or introduced into a sys- tem through the interaction of the output drive capabil- ity with the load impedance. gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference in gain error to full scale error is that full scale does not take offset error into account. gain error can be cali- brated out by adjusting the reference voltage. linearity error refers to the uniformity of the voltage change with code change. linearity errors cannot be cal- ibrated out of the system. integral non-linearity error measures the actual voltage output versus the ideal volt- age output adjusted by the gain error for each code. differential non-linearity error measures the maxi- mum actual voltage step versus the ideal voltage step. this measure is unadjusted. table 10-1: registers/bits associated with dac digital code input ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb ( full scale) analog output voltage address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 11fh dacon0 daon daoe ? ? ? ? dars1 dars0 00-- --00 00-- --00 11eh dac da7 da6 da5 da4 da3 da2 da1 da0 0000 0000 0000 0000 86h trisb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 1111 1111 1111 1111 9dh ansel an7 an6 an5 an4 an3 an2 an1 an0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for dac conversion.
pic16c781/782 ds41171a-page 82 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 83 pic16c781/782 11.0 operational amplifier (opa) module the operational amplifier (opa) module can be config- ured as either an opamp or voltage comparator. the opa module has the following features: external connections to all ports gain bandwidth product selectable: -70 khz nom. - 2 mhz nom. low leakage inputs input offset voltage automatic calibration module (acm) input offset voltage calibration at a programma- ble common mode voltage using the dac interrupt-on-change in comparator mode using iocb 11.1 control registers the opacon register, shown in register 11-1, controls the opa module. the calcon register, shown in register 11-2, controls the automatic calibration module. 11.1.1 opacon register the opa module is enabled by setting the opaon bit (opacon<7>). when enabled, the opa forces the output driver of rb3/an7/opa into tri-state to prevent contention between the driver and the opa output. clearing the cmpen bit (opacon,6>) configures the module as an opamp. setting cmpen configures the module as a voltage comparator. the gbwp bit (opacon<0>) controls the speed of the module in both comparator and opamp configurations. setting gbwp results in a gain bandwidth product (gbwp) of 2 mhz typical. clearing gbwp0 results in a gbwp of the opa of 70 khz typical. figure 11-1: opa module block diagram note 1: when the opa module is enabled, the rb3/an7/opa pin is driven by the opamp output, not by the portb driver. refer to the electrical specifications for the opamp output drive capability. 2: in comparator mode (cmpen = 1), an interrupt can be generated using the iocb feature of rb3. rb3 must be pro- grammed as a digital input with iocb enabled. opa ra0/an0/opa+ opaon gbwp cmpen to adc mux ra1/an1/opa- rb3/an7/opa
pic16c781/782 ds41171a-page 84 preliminary ? 2001 microchip technology inc. register 11-1: opamp control register (opacon: 11ch) 11.1.2 calcon register the automatic calibration module (acm) is an internal state machine which performs an input offset voltage calibration (trim) on the opa module (see figure 11-2). calibration is initiated by setting the cal bit (calcon<7>). upon completion of the calibration sequence, the acm will clear the cal bit. if a problem arises in the calibration process, the calerr flag (calcon<6>) will be set to indicate the failure to calibrate. setting calref (calcon<5>) forces calibration at a common mode voltage specified by the output of the dac module. the dac module must be enabled prior to calibration. clearing calref will perform the cali- bration with a common mode voltage of 1.2v. the out- put pin floats during calibration. r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 opaon cmpen ? ? ? ? ? gbwp bit 7 bit 0 bit 7 opaon: opamp enable bit 1 = opamp is enabled 0 = opamp is disabled bit 6 cmpen: comparator mode enable bit 1 = comparator mode 0 = opamp mode bit 5-1 unimplemented: read as ? 0 ? bit 0 gbwp: gain bandwidth product select bits 1 = 2 mhz typ. (fast mode) 0 = 70 khz typ. (slow mode) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note 1: auto calibration must be performed while the module is configured as an opamp (cmpen = 0). performing auto calibra- tion function in the comparator mode may yield unpredictable results. 2: if the internal 1.2v reference is used for the common mode voltage during auto calibration, calref = 0 (calcon<5>), a delay for reference stabilization must be observed before start of calibration. 3: the opa module shares pins with the adc module. performing adc conver- sions on the opa+ or opa- pins may affect opamp stability. 4: when using the dac as a reference for calibration, calref = 1 (calcon<5>), the v dac voltage must be within the spec- ified common mode voltage for the opamp.
? 2001 microchip technology inc. preliminary ds41171a-page 85 pic16c781/782 figure 11-2: auto calibration module block diagram register 11-2: calibration control register (calcon: 110h) opa 0 1 opa- opa+ 0 1 0 1 1.2v nominal dac module calref automatic calibration module opa 0 1 r/s-0 r-0 r/w-0 u-0 u-0 u-0 u-0 u-0 cal calerr calref ? ? ? ? ? bit 7 bit 0 bit 7 cal: start and status bit 1 = initiates a calibration 0 = reserved (cal is cleared by hardware) bit 6 calerr: calibration error indicator bit 1 = error occurred, opamp failed 0 = no error bit 5 calref: calibration voltage select bit 1 = v dac set to desired common voltage reference 0 = 1.2v nominal source (internal voltage source) note: v dac must not exceed opamp maximum common mode voltage. bit 4-0 reserved: do not use legend: s = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 86 preliminary ? 2001 microchip technology inc. 11.2 configuration as opamp or comparator the following example demonstrates calibration of the opa module as an operational amplifier. example 11-1: calibration for opamp mode ;* this code block will configure the opa ;* module as an op amp, 2 mhz gbwp, and ;* calibrated for a common mode voltage of ;* 1.2v. routine returns w=0 if ;* calibration good. banksel opacon ; select bank 2 movlw b ? 10000001 ? ; op amp mode & movwf opacon ; 2 mhz gbwp bcf calcon,calref; set 1.2v bsf calcon,cal ; start cal_loop btfsc calcon,cal ; test for end goto cal_loop ; if not, wait movlw error_flag btfss calcon,calerr; test for error clrw ; if no, return 0 return the following example demonstrates how to configure and calibrate the opa module as a voltage comparator. example 11-2: calibration for comparator mode ;* this code block will configure the opa ;* module as a voltage comparator, slow ;* speed, and calibrated for a common mode ;* voltage of 2.5 v (assumes vdd=5v). ;* routine returns w=0 if calibration good. banksel opacon ; select bank 2 movlw b ? 10000000 ? movwf opacon ; op amp mode, ; slow bsf calcon,calref; common mode=dac movlw h ? 0x80 ? movwf dac ; dac at vdd/2 movlw b ? 10000000 ? movwf dacon0 ; enable dac, ; vdd ref bsf calcon,cal ; start cal_loop btfsc calcon,cal ; test for end goto cal_loop ; if not, wait movlw error_flag btfss calcon,calerr; test for error clrw ; if no, return 0 bsf opacon,cmpen ; comparator mode return 11.3 effects of reset a device reset forces all registers to their reset state. this disables the opa module and clears any calibration. 11.4 opa module performance common ac and dc performance specifications for the opa module: common mode voltage range leakage current input offset voltage open loop gain gain bandwidth product common mode voltage range is the specified voltage range for the opa+ and opa- inputs, for which the opa module will perform to within its specifications. the opa module is designed to operate with input voltages between 0 and v dd -1.4v. behavior for common mode voltages greater than v dd -1.4v, or below 0v, are not guaranteed. leakage current is a measure of the small source or sink currents on the opa+ and opa- inputs. to mini- mize the effect of leakage currents, the effective imped- ances connected to the opa+ and opa- inputs should be kept as small as possible and equal. input offset voltage is a measure of the voltage differ- ence between the opa+ and opa- inputs in a closed loop circuit with the opa in its linear region. the offset voltage will appear as a dc offset in the output equal to the input offset voltage, multiplied by the gain of the cir- cuit. the input offset voltage is also affected by the common mode voltage. the opa has an automatic calibration module which can minimize the input offset voltage of the module. open loop gain is the ratio of the output voltage to the differential input voltage, (opa+) - (opa-). the gain is greatest at dc and falls off with frequency. gain bandwidth product or gbwp is the frequency at which the open loop gain falls off to 0 db. the lower gbwp is optimized for systems requiring low fre- quency response and low power consumption.
? 2001 microchip technology inc. preliminary ds41171a-page 87 pic16c781/782 table 11-1: registers associated with the opa module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 11ch opacon opaon cmpen ? ? ? ? ? gbwp 00-- ---0 00-- ---0 110h calcon cal calerr calref ? ? ? ? ? 000- ---- 000- ---- 9dh ansel an7 an6 an5 an4 an3 an2 an1 an0 1111 1111 1111 1111 86h trisb portb data direction register 1111 1111 1111 1111 85h trisa porta data direction register 1111 1111 1111 1111 11eh dac da7 da6 da5 da4 da3 da1 da1 da0 0000 0000 0000 0000 11fh dacon0 daon daoe ? ? ? ? dars1 dars0 00-- --00 00-- --00 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for the opa module.
pic16c781/782 ds41171a-page 88 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 89 pic16c781/782 12.0 comparator module the comparator module has two separate voltage com- parators: comparator c1 and comparator c2 (see figure 12-1). each comparator offers the following list of features: control and configuration register comparator output available externally programmable output polarity interrupt-on-change flags wake-up from sleep configurable as feedback input to the psmc programmable four input multiplexer programmable reference selections programmable speed output synchronization to timer1 clock input (comparator c2 only) 12.1 control registers both comparators have separate control and configura- tion registers: cm1con0 for c1 and cm2con0 for c2. in addition, comparator c2 has a second control regis- ter, cm2con1, for synchronization control and simul- taneous reading of both comparator outputs. 12.1.1 comparator c1 control register the cm1con0 register (shown in register 12-1) con- tains the control and status bits for the following: comparator enable comparator input selection comparator reference selection output mode comparator speed setting c1on (cm1con0<7>) enables comparator c1 for operation. bits c1ch<1:0> (cm1con0<1:0>) select the compar- ator input from the four analog pins an<7:4>. setting c1r (cm1con0<2>) selects the output of the dac module as the reference voltage for the compara- tor. clearing c1r selects the v ref 1 input on the ra3/ an3/v ref 1 pin. the output of the comparator is available internally via the c1out flag (cm1con0<6>). to make the output available for an external connection, the c1oe flag (cm1con0<5>) must be set. if the module is disabled with c1oe set, the output will be driven as shown in table 12-2: the polarity of the comparator output can be inverted by setting the c1pol flag (cm1con0<4>). clearing c1pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 12-2. c1sp (cm1con0<3>) configures the speed of the comparator. when c1sp is set, the comparator oper- ates at its normal speed. clearing c1sp operates the comparator in a slower, low power mode. note: to use an<7:4> as analog inputs, the appropriate bits must be programmed in the ansel register. table 12-1: output state versus input conditions input condition c1pol c1out c1vn > c1vp 0 0 c1vn < c1vp 0 1 c1vn > c1vp 1 1 c1vn < c1vp 1 0 note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c1 interrupt will operate correctly with c1oe set or cleared. 3: for the output of c1 on rb6/c1/ psmc1a, the psmc must be disabled and trisb<6> must be ? 0 ? .
pic16c781/782 ds41171a-page 90 preliminary ? 2001 microchip technology inc. figure 12-1: comparator c1 simplified block diagram figure 12-2: comparator c2 simplified block diagram c1 c1pol c1out to interrupt and psmc logic 0 1 2 3 c1on c1sp c1ch<1:0> 2 0 1 v dac c1r c1vp c1vn c1oe rb6/c1/psmc1a rb0/int/an4/v r rb1/an5/v dac rb2/an6 rb3/an7/opa ra3/an3/v ref 1 rb0/int/an4/v r rb1/an5/v dac c2 c2pol c2out to interrupt and psmc logic rb2/an6 rb3/an7/opa 0 1 2 3 c2on c2sp c2ch<1:0> 2 0 1 ra2/an2/v ref 2 v dac c2r 0 1 c2sync from tmr1 clock c2vn c2vp rb7/c2/psmc1b/t1g c2oe d q q
? 2001 microchip technology inc. preliminary ds41171a-page 91 pic16c781/782 register 12-1: comparator c1 control register0 (cm1con0: 119h) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 bit 7 bit 0 bit 7 c1on: comparator c1 enable bit 1 = c1 comparator is enabled 0 = c1 comparator is disabled bit 6 c1out: comparator c1 output bit if c1pol = 1 (inverted polarity): c1out = 1 , c1vp < c1vn c1out = 0 , c1vp > c1vn if c1pol = 0 (non-inverted polarity): c1out = 1 , c1vp > c1vn c1out = 0 , c1vp < c1vn bit 5 c1oe: comparator c1 output enable bit 1 = c1out is present on the rb6/c1/psmc1a pin (1) 0 = c1out is internal only bit 4 c1pol: comparator c1 output polarity select bit 1 = c1out logic is inverted 0 = c1out logic is not inverted bit 3 c1sp: comparator c1 speed select bit 1 = c1 operates in normal speed mode 0 = c1 operates in low power, slow speed mode bit 2 c1r: comparator c1 reference select bits (non-inverting input) 1 = c1vp connects to v dac output 0 = c1vp connects to v ref 1 bit 1-0 c1ch<1:0>: comparator c1 channel select bits 00 = c1vn of c1 connects to an4 01 = c1vn of c1 connects to an5 10 = c1vn of c1 connects to an6 11 = c1vn of c1 connects to an7 note 1: c1out will only drive rb6/c1/psmc1a if: (c2oe = 1) & (c2on = 1) & (trisb<7> = 0) & ((smcon = 0) or ((smcom = 0) & (scen = 0))). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 92 preliminary ? 2001 microchip technology inc. 12.1.2 comparator c2 control registers the cm2con0 register is a functional copy of the cm1con0 register described in section 12.1.1. a sec- ond control register, cm2con1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs. 12.1.2.1 control register cm2con0 the cm2con0 register, shown in register 12-2, con- tains the control and status bits for comparator c2. setting c2on (cm2con0<7>) enables comparator c2 for operation. bits c2ch<1:0> (cm2con0<1:0>) select the compar- ator input from the four analog pins, an<7:4>. c2r (cm2con0<2>) selects the reference to be used with the comparator. setting c2r (cm2con0<2>) selects the output of the dac module as the reference for the comparator. clearing c2r selects the v ref 2 input on the ra2/an2/v ref 2 pin. the output of the comparator is available internally via the c2out bit (cm2con0<6>). to make the output available for an external connection, the c2oe bit (cm2con0<5>) must be set. the comparator output, c2out, can be inverted by setting the c2pol bit (cm2con0<4>). clearing c2pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 12-3. c2sp (cm2con0<3>) configures the speed of the comparator. when c2sp is set, the comparator oper- ates at its normal speed. clearing c2sp operates the comparator in low power mode. note 1: to use an<7:4> as analog inputs, the appropriate bits must be programmed in the ansel register. note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c2 interrupt will operate correctly with c2oe set or cleared. an external output is not required for the c2 interrupt. 3: for c2 output on rb7/c2/psmc1b/t1g : (c2oe=1) & (c2on=1) & (trisb<7>=0) & ((smcon=0) or ((smcom=0) & (scen=0))).
? 2001 microchip technology inc. preliminary ds41171a-page 93 pic16c781/782 register 12-2: comparator c2 control register0 (cm2con0: 11ah) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 bit 7 bit 0 bit 7 c2on: comparator c2 enable bit 1 = c2 comparator is enabled 0 = c2 comparator is disabled bit 6 c2out: comparator c2 output bit if c2pol = 1 (inverted polarity): c2out = 1 , c2vp < c2vn c2out = 0 , c2vp > c2vn if c2pol = 0 (non-inverted polarity): c2out = 1 , c2vp > c2vn c2out = 0 , c2vp < c2vn bit 5 c2oe: comparator c2 output enable bit 1 = c2out is present on rb7/c2/psmc1b/t1g (1) 0 = c2out is internal only bit 4 c2pol: comparator c2 output polarity select bit 1 = c2out logic is inverted 0 = c2out logic is not inverted bit 3 c2sp: comparator c2 speed select bit 1 = c2 operates in normal speed mode 0 = c2 operates in low power, slow speed mode. bit 2 c2r: comparator c2 reference select bits (non-inverting input) 1 = c2vp connects to v dac 0 = c2vp connects to v ref 2 bit 1-0 c2ch<1:0>: comparator c2 channel select bits 00 = c2vn of c2 connects to an4 01 = c2vn of c2 connects to an5 10 = c2vn of c2 connects to an6 11 = c2vn of c2 connects to an7 note 1: c2out will only drive rb7/c2/psmc1b/t1g if: (c2oe = 1) & (c2on = 1) & (trisb<7> = 0) & ((smcon = 0) or ((smcom = 0) & (scen = 0))). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 94 preliminary ? 2001 microchip technology inc. 12.1.2.2 control register cm2con1 comparator c2 has one additional feature: its output can be synchronized to the timer1 clock input. setting c2sync (cm2con1<0>) synchronizes the output of comparator 2 to the falling edge of timer 1 ? s clock input (see figure 12-1 and register 12-3). the cm2con1 register also contains mirror copies of both comparator outputs, mc1out and mc2out (cm2con1<7:6>). the ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. register 12-3: comparator c2 control register1 (cm2con1: 11bh) r-0 r-0 u-0 u-0 u-0 u-0 u-0 r/w-0 mc1out mc2out ? ? ? ? ? c2sync bit 7 bit 0 bit 7 mc1out: mirror copy of c1out (cm1con0<6>) bit 6 mc2out: mirror copy of c2out (cm2con0<6>) bit 5-1 unimplemented: read as ? 0 ? bit 0 c2sync: c2 output synchronous mode bit 1 = c2 output is synchronous to falling edge of tmr1 clock 0 = c2 output is asynchronous legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 95 pic16c781/782 12.2 comparator configuration the following examples show the use of the compara- tor module in: a simple voltage comparator configuration syn- chronized to the timer 1 clock input. a comparator input to the psmc with a program- mable dac reference. a low power window comparator configuration with interrupt-on-change. 12.2.1 example: c2 synchronized to t1cki in this example, comparator c2 is configured as a nor- mal voltage comparator synchronized to the t1cki input. a block diagram of the comparator with external connections is shown in figure 12-2. figure 12-3: comparator c2 configuration with output synchronized to t1cki example 12-1: c2 configuration program ;* this code block will configure c2 ;* for normal speed and output polarity, ;* input on an6, reference from vref2, and ;* output synchronization to tmr1 clock. ;* banksel trisa ; select bank 1 bsf trisa,ra2 ; ra2 as input bsf trisa,ra6 ; ra6 as input bsf trisb,rb2 ; rb2 as input bsf ansel,an2 ; an2 as analog bsf ansel,an6 ; an6 as analog banksel cm2con0 ; select bank 2 movlw b ? 10001010 ? ; set c2; no out movwf cm2con0 ; vref2, an6 bsf cm2con1,c2sync ; clk sync 12.2.2 example: c1 input to psmc w/ dac as reference in this example, comparator c1 is configured as a non- inverting normal speed voltage comparator input to the psmc, with a programmable reference voltage. a block diagram of the comparator with external connec- tions is shown in figure 12-3. d q ck q cm2con0<6> external oscillator external reference input pic16c78x c2 + - rb2/an6 ra2/an2/v ref 2 ra6/osc2/clkout/t1cki c2pol
pic16c781/782 ds41171a-page 96 preliminary ? 2001 microchip technology inc. figure 12-4: configuration of comparator c1 with dac example 12-2: programming c1 for psmc feedback ;* this code block will configure comparator ;* c1 for normal speed and output polarity, ;* input on an7, and reference from the dac banksel trisa ; select bank 1 bsf trisb,rb3 ; rb3 as input bsf ansel,an7 ; set rb3 as analog banksel dacon0 ; select bank 2 clrf dac ; dac=00h movlw b ? 10000000 ? ; enable, no out movwf dacon0 ; dacref = vdd movlw dac_value movwf dac ; trip level movlw b ? 10001111 ? ; c1; no out, movwf cm1con0 ; vref1, an7 12.2.3 example: low power window comparator with interrupt to form a low power window comparator, comparators c1 & c2 are configured as follows: common input rb0/int/an4/v ref separate external reference voltages programmed for slow speed operation in addition, the output of comparator c2 must be inverted for common polarity with c1. a block diagram of the window comparator with exter- nal connections is shown in figure 12-4. figure 12-5: window comparator with interrupt pic16c78x c1 + - rb3/an7/opa c1pol = 0 c1out psmc v dac dac input an4 input c2 + - pic16c78x c1 + - clpol=1 cm2con1<6> cm2con1<7> voltage reference v ref 2 v ref 1 clpol=0
? 2001 microchip technology inc. preliminary ds41171a-page 97 pic16c781/782 example 12-3: window comparator ;* example of low power window comparator c1 ;* this code block will configure comparator ;* c1 and c2 for slow speed, c1 non invert, ;* c2 invert, input on an4, and external ;* references ;* ;* interrupt service routine included ;* banksel trisa ; select bank 1 bsf trisa,2 ; ra2 input bsf trisa,3 ; ra3 input bsf trisb,0 ; set rb0 bsf ansel,an2 ; ra2 analog bsf ansel,an3 ; ra3 analog bsf ansel,an4 ; rb4 analog banksel cm1con0 ; select bank 2 movlw b ? 10000000 ? ; c1: no output movwf cm1con0 ; vref1, an4 movlw b ? 10010000 ? ; c2: no output movwf cm2con0 ; invert,vref1,an4 banksel pie1 ; select bank 1 bcf intcon,gie ; disable int bsf pie1,c1ie ; enabl c1&c2 ints bsf pie1,c2ie bsf intcon,peie bsf intcon,gie ; enabl global ints ;******************************************** ;* window comparator isr with context save wc_int_srv_r movwf w_save ; save w & status swapf status,w movwf status_sav banksel pir1 ; select bank 0 movlw b ? 00110000 ? ; save int andwf pir1,w movwf win_int ;*** clear c1 interrupt btfss win_int,c1if; c1 int ? goto tst_c2_int banksel cm1con0 ; select bank 2 movf cm1con0,f ; clear c2 mismatch banksel pir1 ; select bank 0 bcf pir1,c1if ; clear c2 int ;*** clear c2 interrupt txt_c2_int btfss win_int,c2if; c2 int? goto user_isr banksel cm2con0 ; select bank 2 movf cm2con0,f ; clear c2 mismatch banksel pir1 ; select bank 0 bcf pir1,c1if ; clear c2 int user_isr ;*** user interrupt routing ;* swapf status_save,w; restore w & ; status movwf status swapf w_save,f swapf w_save,w retfie ; return
pic16c781/782 ds41171a-page 98 preliminary ? 2001 microchip technology inc. 12.3 effects of reset a reset forces all registers to their reset state. this disables both comparators. table 12-2: registers associated with the comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 11bh cm2con1 mc1out mc2out ? ? ? ? ? c2sync 00-- ---0 00-- ---0 85h trisa porta data direction register 1111 1111 1111 1111 86h trisb portb data direction register 1111 1111 1111 1111 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 uuuu 0000 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0000 uuuu 0000 9dh ansel an7 an6 an5 an4 an3 an2 an1 an0 1111 1111 1111 1111 0ch pir1 lvdif adif c2if c1if ? ? ? tmr1on 0000 ---0 0000 ---0 8ch pie1 lvdie adie c2ie c1ie ? ? ? tmr1ie 0000 ---0 0000 ---0 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for comparator.
? 2001 microchip technology inc. preliminary ds41171a-page 99 pic16c781/782 13.0 programmable switch mode controller (psmc) the programmable switch mode controller module provides all the necessary features to implement a pulsed feedback control system. the psmc generates a pulse output based on its analog feedback. feedback from the comparator is programmable, allowing: single or dual channel feedback programmable reference voltage selection programmable polarity the pulse output of the psmc is also programmable, featuring either pulse width (pwm) or pulse skip (psm) modulation. in psm, a fixed duty cycle is gener- ated or skipped, based on feedback. in pwm a feed- back controlled pulse width is generated. in addition, the output configuration of the psmc is programmable, enabling the following features: a single output a single output plus a slope compensation output dual alternating outputs all pulse start and duty cycle limit timing features of the psmc are derived from the internal cpu clock. block diagrams for the psmc are shown in figure 13-1 through figure 13-3. 13.1 pulse width modulation (pwm) in the pwm mode, the psmc (shown in figure 13-1 and figure 13-2) is a timer-driven set/reset pulse generator. pulses are initiated by the internal counter chain. following the completion of the programmable minimum duty cycle, the output pulse is terminated by either a high to low transition on the comparator output, or by the programmable maximum duty cycle (see table 13-1 and table 13-2). the resulting output is a variable duty cycle pulse with: programmable frequency feedback specified duty cycle programmable minimum duty cycle including 0% programmable maximum duty cycle figure 13-1: psmc module in single output pwm mode (simplified block diagram) high impedance 1:1 1:2 1:4 1:8 3210 s1 s0 f osc smccl1 smccl0 psmc 4-bit counter clk psmc controller new cycle max dc sc mindc<1:0> maxdc<1:0> 4 2 2 s r q set dominant c1 c1pol c1out smccs c2 c2pol c2out s1apol rb6/c1/psmc1a rb7/c2/psmc1b/t1g n v dd switch scen comparator module new cycle max d/c sc switch min dc period c1out rb6/c1/ psmc1a rb7/c2/ psmc1b/t1g assumes s1apol=0 scen=1 pwm/psm =1 smccs=0 smcon=1 smcom=0 dc = duty cycle example high impedance
pic16c781/782 ds41171a-page 100 preliminary ? 2001 microchip technology inc. figure 13-2: psmc module in dual alternating output pwm mode (simplified block diagram) table 13-1: psmc1a output sequence in pwm mode using c1 comparator only legend: x = don ? t care q = prior state 0 = inactive 1 = active h = high l = low 1:1 1:2 1:4 1:8 3210 s1 s0 f osc smccl1 smccl0 psmc 4-bit counter clk psmc controller new cycle a new cycle b max mindc<1:0> maxdc<1:0> 4 2 2 s r q set dominant c1 c1pol c1out smccs c2 c2pol c2out s1apol rb6/c1/psmc1a dc comparator module s r q set dominant s1bpol new cycle a new cycle b max dc min dc period c1out rb6/c1/ psmc1a rb7/c2/ psmc1b/t1g assumes s1apol=0 smccs=0 pwm/psm =1 s1bpol=0 smcon=1 smcom=1 period min dc min dc dc = duty cycle example rb7/c2/psmc1b/t1g time mindc<1:0> c1out psmc1a output signal beginning of pwm cycle 00 h 0 1 l0 non-zero x 0 1 during min duty cycle non-zero x 1 after min duty cycle, before max duty cycle xh lq 0 l h0 max duty cycle x x q 0
? 2001 microchip technology inc. preliminary ds41171a-page 101 pic16c781/782 table 13-2: psmc1a output sequence in pwm mode using c1 and c2 comparators legend: x = don ? t care q = prior state 0 = inactive 1 = active h = high l = low time mindc<1:0> c1out c2out psmc1a output signal beginning of pwm cycle 00 h h 0 1 lx 0 xl 0 non-zero x x 0 1 during min duty cycle non-zero x x 1 after min duty cycle, before max duty cycle xh lh q 0 l hx 0 hh lq 0 xl h0 max duty cycle x x x q 0
pic16c781/782 ds41171a-page 102 preliminary ? 2001 microchip technology inc. 13.1.1 pulse skip modulation (psm) in psm (pulse skip modulation), the psmc operates as a fixed duty cycle pulse generator, with its output gated by the analog feedback (see figure 13-3). imme- diately prior to the initiation of a pulse, the analog feed- back is sampled. if the comparator output = h, a pulse is initiated and held active for the programmed duty cycle. if the comparator output = l, no pulse is initiated and the psmc waits for the start of the next pulse (see table 13-3 and table 13-4). in this mode, both the fre- quency and duty cycle of the output pulse are program- mable. the analog feedback gates the presence or absence of the pulse on a pulse-by-pulse basis. figure 13-3: psmc module in single output psm mode (simplified block diagram) table 13-3: psmc1a operation in psm mode using c1 comparator only legend: x = don ? t care 0 = inactive 1 = active h = high l = low high impedance :1 :2 :4 :8 3210 s1 s0 f osc smccl1 smccl0 psmc 4-bit counter clk psmc controlle r new cycle max dc sc dc<1:0> 4 2 s r q set dominant c1 c1pol c1out smccs c2 c2pol c2out s1apol n v dd switch scen comparator module new cycle select dc sc switch period c1out rb6/c1/ psmc1a rb7/c2/ psmc1b/t1g assumes s1apol=0 scen=1 pwm/psm =0 smccs=0 smcon=1 smcom=0 programmed dc 15/16 period dc = duty cycle example rb6/c1/psmc1a rb7/c2/psmc1b/t1g high impedance time c1out psmc1a output signal beginning of psm cycle h 0 1 l0 during pulse x no change 1 end of pulse x 1 0
? 2001 microchip technology inc. preliminary ds41171a-page 103 pic16c781/782 table 13-4: psmc1a output sequence in psm mode using c1 and c2 comparators legend: x = don ? t care 0 = inactive 1 = active h = high l = low 13.1.2 single or dual output the psmc has the capability to operate with either a single output, or dual alternating outputs. in the single output mode, the psmc generates an output pulse on psmc1a output only. the pulses are at the pro- grammed frequency, and are variable between the pro- grammed minimum and maximum duty cycle limits. in the dual output mode, the psmc generates output pulses which alternate between psmc1a and psmc1b. the pulses generated at each output are generated at one half of the programmed frequency, and between 50% of the programmed minimum. and 50% maximum of the output duty cycle. the maximum duty cycle for either output is 50%. 13.1.3 slope compensation an optional feature of the psmc single output mode is the ability to configure the psmc1b output for use as a slope compensation ramp generator. in this mode, the psmc1b output is pulled low for the last 1/16 of each pulse cycle. connecting the psmc1b output to an rc network, similar to figure 13-4, results in a positive going pseudo ramp function. this pseudo ramp func- tion is useful as an offset function for the loop error sig- nal in unstable conditions at a duty cycle of greater than 50%. figure 13-4: slope compensation (sc) switch operation time c1out c2out psmc1a output signal beginning of psm cycle h h 0 1 lx 0 xl 0 during pulse duty cycle x x no change x x no change after pulse duty cycle x x 1 0 note: when the slope compensation switch is enabled (smcom = 0, and scen = 1), the s1bpol bit has no effect (see rc network on next page for more detail). pwm signal on psmc1a sc switch on psmc1b voltage across c t = 0 t = 15/16t dc = duty cycle t = period - on - off r c v dd psmc1a psmc1b to slope compensation circuit sc switch psmc module v ss pic16c78x pin pin 150 v dd v ss
pic16c781/782 ds41171a-page 104 preliminary ? 2001 microchip technology inc. 13.2 control registers the psmc is controlled by means of two special func- tion registers: psmccon0 and psmccon1. the psmccon0 register (register 13-1) contains control bits for: frequency of the output pulse minimum and maximum duty cycle in pwm mode fixed duty cycle in psm mode the psmccon1 register (register 13-2) contains the control bits for: enabling the psmc module setting the psmc mode configuring inputs and outputs 13.2.1 psmccon0 register the smccl<1:0> bits in the psmccon0 register, are used to set the pulse frequency of the psmc. in the pwm mode, the mindc <1:0> bits (psmccon0 <5:4>) specify the minimum duty cycle. in the pwm mode, the maxdc <1:0> bits (psmccon0 <3:2>) specify the maximum duty cycle limit. in the psm mode, the dc<1:0> bits (psmccon0<1:0>) specify the fixed duty cycle. 13.2.2 psmccon1 register to enable the psmc operation, the smcon bit in the psmccon1 register must be set (see register 13-2). the pwm/psm bit (psmccon1<1>) configures the output mode of the psmc. when the pwm/psm bit is set, the psmc is configured for a pwm output. when the pwm/psm bit is cleared, a fixed duty cycle pulse is output. the smccs bit (psmccon1<0>) sets the input mode. when the smccs bit is set, the psmc is con- figured for two inputs: c1 and c2. when cleared, only comparator c1 is used. smcom bit (psmccon1<1>) determines the number of outputs from the psmc. when smcom is set, both psmc1a and psmc1b are active. when smcom is cleared, only the psmc1a output is active and the psmc1b output is available for another function. s1apol and s1bpol control the polarity of the psmc outputs. setting the polarity bit configures the corre- sponding output for an active low state. clearing the bit results in an active high output. the scen bit (psmccon1<2>) enables the slope compensation output. when scen is set (and smcom is cleared) the psmc1b output is configured to gener- ate a slope compensation signal. table 13-5: psmc output modes legend: x = don ? t care *as needed for other functions (such as c2, rb7, t1g ). note: following reset, both the psmc1a and psmc1b outputs are held tri-state until the psmc is configured. driver circuitry for all power mosfet transistors must have a resistor bias to turn off the transistor in the event of tri-state conditions, on either psmc1a or psmc1b, to prevent exces- sive stress on the mosfet's and their associated circuitry. note: changing smccl<1:0> bits with the psmc enabled (smcon=1) can result in unpredictable output. always disable psmc before changing smccl<1:0>. note: psmc outputs must have their corre- sponding direction bits cleared in trisb; trisb<6>: for psmc1a, and trisb<7> for psmc1b. function psmc portb smcom scen trisb<6> trisb<7> single output 0 0 0 * single output + slope compensation 0 1 0 0 dual output 1 x 0 0
? 2001 microchip technology inc. preliminary ds41171a-page 105 pic16c781/782 register 13-1: psmc control register0 (psmccon0: 111h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 smccl1 smccl0 mindc1 mindc0 maxdc1 maxdc0 dc1 dc0 bit 7 bit 0 bit 7-6 smccl<1:0>: clock frequency select bits 00 = output frequency for single output mode is f osc /128 01 = output frequency for single output mode is f osc /64 10 = output frequency for single output mode is f osc /32 11 = output frequency for single output mode is f osc /16 bit 5-4 mindc<1:0>: minimum duty cycle select bits for pwm mode 00 = min duty cycle of 0 01 = min duty cycle of 1/8 10 = min duty cycle of 1/4 11 = min duty cycle of 3/8 bit 3-2 maxdc<1:0>: maximum duty cycle select bits for pwm mode 00 = max duty cycle of 1/2 01 = max duty cycle of 5/8 10 = max duty cycle of 3/4 11 = max duty cycle of 15/16 bit 1-0 dc<1:0>: duty cycle select bits for psm mode 00 = duty cycle of 1/8 01 = duty cycle of 3/8 10 = duty cycle of 5/8 11 = duty cycle of 15/16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c781/782 ds41171a-page 106 preliminary ? 2001 microchip technology inc. register 13-2: psmc control register1 (psmccon1: 112h) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 smcon s1apol s1bpol ? scen smcom pwm/psm smccs bit 7 bit 0 bit 7 smcon: psmc module enable bit 1 = psmc module on 0 = psmc module off bit 6 s1apol: psmc1a output polarity control bit 1 = psmc1a output signal is asserted low 0 = psmc1a output signal is asserted high bit 5 s1bpol: psmc1b output polarity control bit 1 = psmc1b output signal is asserted low 0 = psmc1b output signal is asserted high bit 4 unimplemented: read as ? 0 bit 3 scen: slope compensation output enable bit if smcom = 1: x = this bit is ignored if smcom = 0: 1 = slope compensation switch on psmc1b pin is enabled 0 = slope compensation switch on psmc1b pin is not enabled. psmc1b pin is available for other functions. bit 2 smcom: psmc output mode bit 1 = dual alternating output mode. the module outputs are available on the psmc1a and psmc1b pins. 0 = single output mode. the module output is available on the psmc1a pin. bit 1 pwm/psm : psmc modulation mode select bit 1 = pwm mode (pulse width modulation) 0 = psm mode (pulse skipping modulation) bit 0 smccs: psmc comparator select bit 1 = psmc module uses inputs from both c1out and c2out 0 = smc module uses input from c1out only legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41171a-page 107 pic16c781/782 13.3 configuration the programmable nature of the psmc lends itself to a wide variety of applications involving current or voltage management. the following examples are intended to provide suggested applications for the psmc. the examples are not complete designs, but rather block diagrams of some potential applications of the psmc. for a broader list of applications, including supporting math and firmware examples, please refer to microchip web page for applicable application notes. 13.3.1 example boost lc switching power supply in this example, the psmc controls the boost configu- ration switching power supply in figure 13-5. the psmc is configured as a two feedback loop pwm, current mode, switching power supply controller. the inner current feedback loops consist of: psmc mosfet driver power mosfet q1 inductor l1 current transformer comparator c1 the outer voltage feedback loop consists of: diode d1 c main opamp feedback filter dac reference the inner current loop is a pulsed current source driven by the psmc. during the active phase of the output pulse, the inner loop builds up a current flow in inductor l1. the current in l1 is monitored by the current trans- former. the output of the transformer is offset by the ramp from the slope compensation network r3/c1 and then fed into the comparator. when the voltage (pro- portional to the current flow in l1, offset by the slope compensation) exceeds the error voltage from the opamp, q1 is turned off and l1 discharges through d1 into c main for the remainder of the period. the outer voltage loop monitors the output voltage across c main using r1/r2. the reference voltage from the dac is subtracted, generating the raw error volt- age. the raw error voltage is filtered by the opamp and routed to comparator c1 in the inner current loop. the phase compensation output of the psmc acts to improve loop stability by adding a pseudo-ramp wave- form to the current sense transformer feedback in the inner loop. in conditions where the charge phase of the cycle is greater then 50%, the increased current feed- back reduces the current charge in l1, slowing the charging of c main . the result is a reduction in the over- all loop gain for duty cycles of >50%, maintaining loop stability.
pic16c781/782 ds41171a-page 108 preliminary ? 2001 microchip technology inc. figure 13-5: example boost configuration lc switching power supply l 1 + driver +dcraw v dd ra1/an1/opa- ra4/an0/opa+ rb2/an6 psmc a sc dac pic16c781/782 opa c1 q1 d1 c main v ref rb6/c1/psmc1a rb7/c2/psmc1b rb3/an7/opa ra3/an3/v ref 1 rb1/an5/v dac mosfet load current transformer r 3 c 1 r 1 r 2 note: the opamp, comparator and dac must be configured, prior to enabling the psmc to prevent unpredictable operation which may stress the power mosfet transistors.
? 2001 microchip technology inc. preliminary ds41171a-page 109 pic16c781/782 example 13-1: psmc configuration example ;* this code block will configure the psmc and ;* all additional peripherals for a boost mode ;* switching power supply. ;* ;* order of configuration ;* 1. porta/b i/o and analog configured ;* 2. dac enabled, configured, and preset ;* 3. op amp enabled and configured ;* 4. comparator c1 enabled and configured ;* 5. psmc configured ;* 6. psmc enabled ********************************************************** ;* this code block will configure all analog ports. banksel trisa ; select bank 1 movlw b ? 00001011 ? movwf trisa ; set ra0,1,& 3 as inputs movlw b ? 11001110 ? movwf trisb ; set rb1,2,3,6 & 7 as inputs movlw b ? 11101011 ? ; configure ra0, ra1, ra3, movwf ansel ; rb1, rb2, rb3 as analog ;********************************************************************** ;* this code block will configure the dac for vdd as ;* dacref, and rb1/an5/vdac as an output banksel dacon0 ; select bank 2 clrf dac ; set dac to safe value movlw b ? 11000000 ? ; enable dac, output movwf dacon0 ; and set dacref = vdd movlw output_value movwf dac ; set dac output level ;********************************************************************** ;* this code block will configure the opa module as an ;* op amp, with a 2mhz gbwp movlw b ? 10000001 ? ; set op amp mode and movwf opacon ; 2mhz gbwp ;************************************************************************* ;* this code block will configure comparator c1 ;* for normal speed and output polarity, ;* input on an6, and reference from the vref1 movlw b ? 10001010 ; set c1, no ext out, norm movwf cm1con0 ; speed & pol, vref1, an6 ;************************************************************************ ;* this code block will configure the psmc module ;* for pwm, fosc/128, single in, single pulse out, slope comp out ;* non-inverting out, dc min = 0%, dc max = 75% movlw b ? 00001000 ? movwf psmccon0 ; set dcmin 0, dcmax 75, fosc/128 movlw b ? 00001010 ? ; set pwm sngl in, sngl out non-invert movwf psmccon1 ; slope comp bsf psmccon1,smcon ; enable psmc
pic16c781/782 ds41171a-page 110 preliminary ? 2001 microchip technology inc. 13.3.2 example buck lc switching power supply in this example, the psmc controls the buck configura- tion switching power supply in figure 13-6. the psmc is configured as a typical pwm, current mode, switching power supply controller. the inner cur- rent feedback loops consist of: psmc 2 mosfet drivers power mosfets q1 and q2 inductors l1 and l2 current transformer comparator c1/c2 the outer voltage feedback loop consists of: diodes d1, d2, d3, and d4 c main opamp feedback filter dac reference the circuit uses two feedback loops, an inner current control loop, and an outer voltage loop. the inner loop is further divided into two channels, q1/l1, and q2/l2. the psmc operates a pwm output, alternately driving q1 for a cycle, then driving q2 the next. during the active phase of either output pulse, the inner loop builds up a current flow in the output ? s inductor, propor- tional to the error voltage received from the opamp. the current flow in the inductor begins the charging of c main . when the voltage (proportional to the current flow in the inductor) exceeds the error voltage: the comparator resets the psmc output the mosfet is turned off the flyback diode forward biases the inductor discharges into c main for the remainder of the period. the outer voltage loop monitors the output voltage across c main via r1/r2. the reference voltage from the dac is subtracted from the feedback voltage to generate the raw error voltage. the raw error voltage is then filtered by the opamp and routed to comparator c1 in the inner current loop. in using two alternating outputs, the outputs are limited to less than 50% duty cycle. as a result, the circuit avoids the problems associated with instability at duty cycles of >50%. for more information concerning the design of switch- ing power supplies, refer to: switching power supply design, by abraham i. press- man, published by mcgraw hill (isbn 0-07-052236-7). note: following reset, both the psmc1a and psmc1b outputs are held tri-state until the psmc is configured. driver circuitry for all power mosfet transistors must have a resistor bias to turn off the transistor in the event of tri-state conditions on either out- put to prevent undo stress on the mos- fet's and their associated circuitry.
? 2001 microchip technology inc. preliminary ds41171a-page 111 pic16c781/782 example 13-2: example psmc configuration for a buck mode switching power supply ;* psmc initialization ;* this code block will configure the psmc ;* and all additional peripherals for a buck ;* mode switching power supply. ;* ;* order of configuration ;* 1. porta/b i/o and analog configured ;* 2. dac enabled, configured, and preset ;* 3. op amp enabled and configured ;* 4. comparator c1 enabled and configured ;* 5. psmc configured ;* 6. psmc enabled ;******************************************** ;* this code block will configure all analog ports. ; banksel trisa ; select bank 1 movlw b ? 00001011 ? movwf trisa ; set ra0,1,& 3 as inputs movlw b ? 11001110 movwf trisb ; set rb1,2,3,6 & 7 as inputs movlw b ? 11101011 ? movwf ansel ; set an0,1,3,5,6 & 7 as analog ;******************************************************* ;* this code block will configure the dac for vdd as ;* dacref, and rb1/an5/vdac as an output. banksel dacon0 ; select bank 2 clrf dac ; set dac to safe value movlw b ? 11000000 ? ; enable dac, output movwf dacon0 ; and set dacref = vdd movlw output_value movwf dac ; set dac output level ;******************************************************* ;* this code block will configure the opa module ;* as an op amp, with a 3 mhz gbwp movlw b ? 10000001 ? ; set op amp mode and movwf opacon ; 2 mhz gbwp ;******************************************************** ;* this code block will configure comparator c1 ;* for normal speed and output polarity, ;* input on an6, and reference from the vref1 movlw b ? 10001010 ? ; set c1; no ext out, norm movwf cm1con0 ; speed & pol, vref1, an6 ;******************************************************** ;* this code block will configure the psmc module ;* for pwm, fosc/128, single input, single output ;* non-inverting out, dc min = 0%, dc max = 50% movlw b ? 0000000 ? movwf psmccon0 ; set dcmin 0, dcmax 50, fosc/128 movlw b ? 00000110 ? movwf psmccon1 ; set pwm, 1 in, 2 out, noninvert bsf psmccon1,smcon ; enable psmc
pic16c781/782 ds41171a-page 112 preliminary ? 2001 microchip technology inc. figure 13-6: example buck configuration lc power supply 13.3.3 example motor speed control in figure 13-7, the psmc acts as a speed control for a brushless dc motor. the direction of the current in the motor winding is set by feedback from a hall effect position sensor on the motor. the sensor switches the phase in the motor in response to the rotation of the rotor so that the magnetic field rotates just ahead of the rotor, pulling it in the desired direction. the speed at which the rotor spins is a function of the mechanical load on the rotor and the current in the field winding. speed control is accomplished by monitoring the speed via the hall effect sensor and regulating the current in the winding appropriately. the winding current is regu- lated by the psmc to be proportional to the value sup- plied by the dac module. the feedback loop is closed by software making periodic measurement of the rotor speed using the hall effect sensor/timer1 and adjust- ing the output value of the dac appropriately. the algorithm (used to determine the values output by the dac module) depends on: mechanical system connected to the motor motor characteristics characteristics of the high current drive an analysis of the mechanics of the system and the design of an appropriate control algorithm is beyond the scope of this data sheet. therefore, the designer should consult a text dealing with the design of motor speed controls and feedback control system, in general, for the necessary design guidance. +v in rb6/c1/psmc1a a dac pic16c781/782 c1 ra3/an3/v ref 1 v ref l1 d1 q1 q2 current transformer b mosfet l2 d3 d4 load driver driver mosfet + - rb7/c2/psmc1b/t1g rb2/an6 opa + - rb3/an7/opa ra1/an1/opa- ra0/an0/opa+ rb1/an5/v dac d2 c main r1 r2 psmc
? 2001 microchip technology inc. preliminary ds41171a-page 113 pic16c781/782 example 13-3: peripheral configuration example ************************************************ ;* this code block will configure the psmc and ;* all additional peripherals for a motor speed ;* control. ;* ;* order of configuration ;* 1. porta/b i/o and analog configured ;* 2. dac enabled, configured, and preset ;* 3. op amp enabled and configured ;* 4. comparator c1 enabled and configured ;* 5. psmc configured ;* 6. psmc enabled ;* ************************************************ ;* this code block will configure all analog ports. banksel trisa ; select bank 1 movlw b ? 01000011 ? movwf trisa ; set ra0,1 & 6 as inputs movlw b ? 00001100 ? movwf trisb ; set rb2 & 3 as inputs movlw b ? 11000011 ? movwf ansel ; set an0,1,6,& 7 as analog ;************************************************ ;* this code block will configure the dac for vr as ;* dacref, and no output. banksel refcon bsf refcon, vren ; enable vr banksel dacon0 ; select bank 2 clrf dac ; set dac to safe value movlw b ? 10000010 ? ; enable dac, no output movwf dacon0 ; and set dacref = vr movlw output_value movwf dac ; set dac output level ;************************************************ ;* this code block will configure the opa module ;* as an op amp, with a 2 mhz gbwp movlw b ? 10000001 ? ; set op amp mode and movwf opacon ; 2 mhz gbwp ;************************************************ * this code block will configure comparator c1 * for normal speed and output polarity, * input on an6, and reference from the vdac movlw b ? 10001110 ? ; set c1; no ext out, norm movwf cm1con0 ; speed & pol, vdac, an6 ;************************************************ ;* this code block will configure the psmc module ;* for pwm, fosc/16, single input, single output ;* non-inverting out, dc min = 0%, dc max = 94% movlw b ? 11001100 ? movwf psmccon0 ; set dcmin 0, dcmax 94, fosc/16 movlw b ? 00000010 ? movwf psmccon1 ; set pwm, sngl in/out, noninvert bsf psmccon1,smcon ; enable psmc
pic16c781/782 ds41171a-page 114 preliminary ? 2001 microchip technology inc. figure 13-7: example brushless d.c. motor control r sense /16 f osc s q r dac pic16c781/782 c1 h-bridge driver enable phase brushless d.c. motor hall effect sensor timer 1 firmware feedback control v motor ra0/an0/opa+ ra1/an1/opa- opa v ref rb6/c1/psmc1a rb2/an6 rb3/an7/opa ra6/osc2/clkout/t1cki
? 2001 microchip technology inc. preliminary ds41171a-page 115 pic16c781/782 13.4 effects of sleep and reset a device reset forces all registers to their reset state. this disables the psmc and resets its outputs to digital inputs. it is good design practice to include a fail- safe resistor bias in all power transistor drive circuitry. the fail-safe circuit should disable the power device when the psmc output drive transistor is held tri-state. this protects the power device and its associated cir- cuitry from the stress of prolonged operation without feedback. placing the pic16c781/782 into sleep mode will stop the main oscillator for the microcontroller. the psmc derives its timing from the main oscillator. therefore, operation of the psmc will halt when the microcontrol- ler enters sleep mode. to prevent damage, the out- puts of the psmc are gated so that they are driven to their inactive state whenever the device enters sleep mode. when the microcontroller wakes up, the psmc resumes operation per its previously programmed con- figuration. table 13-6: registers associated with the psmc address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 86h,186h trisb portb data direction register 1111 1111 1111 1111 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 111h psmccon0 smccl1 smccl0 mindc1 mindc0 maxdc1 maxdc0 dc1 dc0 0000 0000 0000 0000 112h psmccon1 smcon s1apol s1bpol ? scen smcom pwm/psm smccs 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for psmc.
pic16c781/782 ds41171a-page 116 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 117 pic16c781/782 14.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection. these fea- tures include: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - programmable brown-out reset (pbor) interrupts watchdog timer (wdt) programmable low voltage detection (plvd) sleep code protection id locations in-circuit serial programming tm (icsp tm ) several oscillator options are available to allow the part to fit the application. the intrc oscillator options save system cost while the lp crystal option saves power. a set of configuration bits is used to select various options. the cpu also features a watchdog timer (wdt), which can be enabled either through a configuration bit during programming, or by the software. for added reli- ability, the wdt runs off its own internal rc oscillator instead of the main cpu clock. in addition to the wdt, the cpu incorporates both an oscillator start-up timer and a power-up timer. the oscillator start-up timer (ost) is intended to hold the chip in reset until the crystal oscillator has stabilized. the power-up timer (pwrt) holds the cpu in a fixed reset delay of 72ms (nominal) on power-up resets (por and pbor), while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can awaken from sleep through: external reset watchdog timer wake-up interrupt additional information on special features is available in the picmicro ? mid-range reference manual, (ds33023). 14.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped in pro- gram memory location 2007h. some of the core features provided may not be neces- sary for each application in which a device may be used. the configuration word bits allow these features to be configured/enabled/disabled as necessary. these features include: code protection pbor trip point power-up timer watchdog timer device oscillator mode as can be seen in table 14-1, some additional configu- ration word bits have been provided for brown-out reset trip point selection. note: address 2007h is beyond the user pro- gram memory space, which can be accessed only during programming.
pic16c781/782 ds41171a-page 118 preliminary ? 2001 microchip technology inc. register 14-1: configuration word for pic16c781/782 device (config:2007h) cp cp borv1 borv0 cp cp ? boden mclre pwrte wdte f0sc2 f0sc1 f0sc0 bit13 bit0 bit 13-12, 9-8 cp: program memory code protection bits 1 = code protection off 0 = all program memory is protected (1) bit 11-10 borv<1:0>: brown-out reset voltage bits 00 = pbor set to 4.5v 01 = pbor set to 4.2v 10 = pbor set to 2.7v 11 = pbor set to 2.5v bit 7 unimplemented: read as ? 1 ? bit 6 boden : brown-out detect reset enable bit (1) 1 = brown-out detect reset enabled 0 = brown-out detect reset disabled bit 5 mclre: ra5/mclr pin function select bit 1 = ra5/mclr pin function is mclr 0 = ra5/mclr pin function is digital input, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<2:0> : oscillator selection bits note 1: all of the cp bits must be given the same value to enable code protection. fosc<2:0> oscillator ra6/osc2/clkout/t1cki ra7/osc1/clkin 000 lp crystal/resonator crystal/resonator 001 xt crystal/resonator crystal/resonator 010 hs crystal/resonator crystal/resonator 011 ec digital i/o clkin 100 intrc digital i/o digital i/o 101 intrc clkout digital i/o 110 rc digital i/o rc 111 rc clkout rc
? 2001 microchip technology inc. preliminary ds41171a-page 119 pic16c781/782 14.2 oscillator configurations 14.2.1 oscillator types the pic16c781/782 can be operated in eight different oscillator modes. the user can program three configu- ration bits fosc<2:0> to select one of these eight modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc external resistor and capacitor (with and without clkout) intrc internal 4 mhz/37 khz (with and without clkout) ec external clock 14.2.2 lp, xt and hs modes in lp, xt, or hs modes, a crystal or ceramic resonator is connected to the ra7/osc1/clkin and ra6/osc2/ clkout/t1cki pins to establish oscillation (figure 14-1). the pic16c781/782 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may yield a frequency outside of the crystal manufacturers ? specifications. figure 14-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) table 14-1: ceramic resonators table 14-2: capacitor selection for crystal oscillator 14.2.3 ec mode in applications where the clock source is external, the pic16c781/782 should be programmed to select the ec (external clock) mode. in this mode, the ra6/ osc2/clkout/t1cki pin is available as an i/o pin. see figure 14-2 for illustration. to minimize power sup- ply current drawn, the ec oscillator input should be driven by a cmos level square wave. note 1: see table 14-1 and table 14-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal r f (3) sleep to logic pic16c781/782 rs (2) internal ra7/osc1/ clkin ra6/osc2 clkout/ t1cki ranges tested: mode freq c1 c2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes 1 and 2 in shaded box. in this test, all resonators used did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes 1 and 2 in shaded box. note 1: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 2: higher capacitance increases the stability of oscillator but also increases the start-up time.
pic16c781/782 ds41171a-page 120 preliminary ? 2001 microchip technology inc. figure 14-2: ec osc configuration 14.2.4 rc mode for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of: supply voltage resistor (r ext ) and capacitor (c ext ) values operating temperature in addition, the oscillator frequency varies from unit to unit due to normal process variation. the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low c ext values. the user should allow for variations due to tolerance of external r and c components used. figure 14-3 shows how the rc combination is con- nected to the pic16c781/782. for r ext values below 2.2 k ? , the oscillator operation may become unstable or stop completely. for very high r ext values (e.g., 1 m ? or greater), the oscillator becomes sensitive to: noise humidity leakage microchip recommends keeping r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as board trace capacitance or package lead frame capacitance. see section 18.0 for rc frequency variation from part to part due to normal process variation. the variation is greater for large values of r (since leakage current variations affect rc frequency more for large r) and for small values of c (since variations of input capacitance affect rc frequency more). see section 18.0 for variation of oscillator frequency due to v dd for given r ext and c ext values (or for fre- quency variation due to operating temperature for given r, c, and v dd values). figure 14-3: rc oscillator mode 14.2.5 intrc mode the internal rc oscillator provides a fixed 4 mhz/37 khz (nominal) system clock at v dd = 5v and 25 c. see section 18.0 for information on variations over voltage and temperature ranges. the intrc oscillator does not run during reset. 14.2.6 dual speed operation for intrc mode a software programmable slow speed mode is avail- able with the intrc oscillator. this feature allows the firmware to dynamically toggle the oscillator speed between normal and slow frequencies. the nominal slow frequency is 37 khz. applications that require low current power savings, but cannot tolerate putting the part into sleep, may use this mode. the oscf bit (pcon<3>) is used to control dual speed mode. see the pcon register, register 2-6, for details. when changing the intrc internal oscillator speed, there is a brief period of time when the processor is inactive. when the speed changes from fast to slow, the processor inactive period is in the range of 100 s to 300 s. for a speed change from slow to fast, the processor is inactive between 1.25 s and 3.25 s, nominal. 14.2.7 clkout in the intrc and rc modes, the pic16c781/782 can be configured to provide a clock out signal by program- ming the configuration word. the oscillator frequency, divided by 4, can be used for test purposes or to syn- chronize other logic. in the intrc and rc modes, if the clkout output is enabled, clkout is held low during reset. ra7/osc1/clkin ra6/osc2/clkout/ i/o clock from ext. system pic16c781/782 ra7 t1cki ra6/osc2/clkout/i1cki c ext v dd r ext v ss pic16c781/782 ra7/osc1/ f osc /4 internal clock clkin
? 2001 microchip technology inc. preliminary ds41171a-page 121 pic16c781/782 14.3 reset the pic16c781/782 devices have several different resets. these resets are grouped into two classi- fications: power-up and non power-up. the power-up type resets are the power-on and brown-out resets, which assume the device v dd was below its normal operating range for the device ? s configuration. the non power-up type resets assume normal oper- ating limits were maintained before/during and after the reset. power-on reset (por) programmable brown-out reset (pbor) non power-up (mclr ) reset during normal operation mclr reset during sleep wdt reset (during normal operation) some registers are not affected in any reset condi- tion. their status is unknown on a power-up reset and unchanged in any other reset. most other registers are placed into an initialized state upon reset. how- ever, they are not affected by a wdt reset during sleep, because this is considered a wdt wake-up, which is viewed as the resumption of normal operation. several status bits have been provided to indicate which reset occurred (see table 14-4). see table 14-5 for a full description of reset states of special registers. a simplified block diagram of the on-chip reset circuit is shown in figure 14-4. these devices have a mclr noise filter in the mclr reset path. the filter detects and ignores small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 14-4: simplified block diagram of on-chip reset circuit s r q external reset v dd ra7/osc1/ wdt module v dd rise detect ost/pwrt dedicated oscillator power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter enable ost enable pwrt sleep brown-out programmable boden time-out ra5/mclr /v pp clkin
pic16c781/782 ds41171a-page 122 preliminary ? 2001 microchip technology inc. 14.4 power-on reset (por) a power-on reset pulse is generated on-chip when a v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, simply enable the internal mclr feature. this eliminates external rc compo- nents usually needed to create a power-on reset. a maximum rise time for v dd is specified. see section 17.0 for details. for a slow rise time, see figure 14-5. two delay timers (pwrt on ost) are provided, which hold the device in reset after a por (dependent upon device configuration), so that all operational parameters have been met prior to releasing the device to resume/begin normal operation. when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating con- ditions are met. brown-out reset may be used to meet the start-up conditions, or if necessary an external por circuit may be implemented to delay end of reset for as long as needed. figure 14-5: external power-on reset circuit (for slow v dd ramp) 14.5 power-up timer (pwrt) the power-up timer provides a fixed t pwrt time-out on power-up type resets only. for a por, the pwrt is invoked when the por pulse is generated. for a bor, the pwrt is invoked when the device exits the reset condition (v dd rises above bor trip point). the power-up timer operates on an internal rc oscil- lator. the chip is kept in reset as long as the pwrt is active. the pwrt ? s time delay is designed to allow v dd to rise to an acceptable level. a configuration bit (p wrt ) is provided to enable/disable the pwrt for the por only. for a bor the pwrt is always available regardless of the configuration bit setting. the power-up time delay varies from chip-to-chip due to v dd , temperature and process variation. see dc parameters for details. 14.6 programmable brown-out reset (pbor) the programmable brown-out reset module is used to generate a reset when the supply voltage falls below a specified trip voltage. the trip voltage is configurable to any one of four voltages provided by the borv<1:0> configuration word bits. configuration bit boden can disable (if clear/pro- grammed), or enable (if set), the brown-out reset cir- cuitry. if v dd falls below the specified trip point for longer than t bor (see parameter 35, section 17.0, table 17-6), the brown-out situation resets the chip. a reset may not occur if v dd falls below the trip point for less than t bor . the chip remains in brown-out reset until v dd rises above v bor . the power-up timer is invoked at that point and keeps the chip in reset an additional t pwrt . if v dd drops below v bor while the power-up timer is running, the chip goes back into a brown-out reset and the power-up timer is re- initialized. once v dd rises above v bor , the power-up timer again begins a t pwrt time delay. 14.7 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked by the por pulse. when the pwrt delay expires, the oscillator start-up timer is activated. the total time-out varies depending on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there is no time-out at all. figure 14-6, and figure 14-9 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs expire. then, bringing mclr high begins execution immediately. this is useful for testing purposes or to synchronize more than one picmicro microcontroller operating in parallel. table 14-5 shows the reset conditions for some spe- cial function registers. note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that voltage drop across r does not violate the device ? s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flow- ing into mclr from external capacitor c in the event of mclr pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16c781/782 v dd
? 2001 microchip technology inc. preliminary ds41171a-page 123 pic16c781/782 14.8 power control/status register (pcon) the power control/status register, pcon, has two status bits that provide indication of which power-up type reset occurred. pcon<0> is brown-out reset status bit, bor . bit bor is set on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a bor occurred. how- ever, if the brown-out circuitry is disabled, the bor bit is a "don ? t care" bit and is considered unknown upon a por. pcon<1> is por (power-on reset status bit). it is cleared on a power-on reset and unaffected other- wise. the user must set this bit following a power-on reset. when the cpu is running under the intrc oscillator mode, the frequency of the intrc oscillator can be switched to a power saving 37 khz (nominal) mode. clearing the oscf (pcon<3>) enables oscillation at 37khz, setting oscf returns the oscillator to operation at 4mhz. the watchdog timer is a free running, on-chip dedi- cated oscillator and timer, which does not require any external components to operate. the wdt provides a system reset in the event that software does not exe- cute a clrwdt instruction within a specified interval. for reliability, the wdt will run even if the cpu clock has been stopped (for example, by the execution of a sleep instruction). during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to awaken and resume normal operation (watchdog timer wake-up). the wdt can be enabled either by setting the wdte bit in the configuration register during programming, or by setting the wdton bit (pcon<4>). table 14-3: time-out in various situations oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024t osc 1024t osc t pwrt + 1024t osc 1024t osc ec, rc, intrc t pwrt ? t pwrt ?
pic16c781/782 ds41171a-page 124 preliminary ? 2001 microchip technology inc. register 14-2: power control register (pcon: 8eh) table 14-4: status bits and their significance u-0 u-0 u-0 r/w-q r/w-1 u-0 r/w-q r/w-x ? ? ? wdton oscf ? por bor bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 wdton: wdt software enable bit if wdte bit (configuration word <3>) = 1: this bit is not writable, always reads ? 1 ? if wdte bit (configuration word <3>) = 0: 1 = wdt is enabled 0 = wdt is disabled and cleared bit 3 oscf: oscillator speed bit (pending on new internal oscillator decision) intrc mode: 1 = 4 mhz typical 0 = 37 khz typical all other oscillator modes: ignored bit 2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? q ? = value depends on condition por bor to pd bit significance 0111 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep
? 2001 microchip technology inc. preliminary ds41171a-page 125 pic16c781/782 table 14-5: reset condition for special registers figure 14-6: time-out sequence on power-up (mclr tied to v dd ) figure 14-7: time-out sequence on power-up (mclr not tied to v dd ) condition program counter status register pcon register power-on reset 000h 0001 1xxx ---0 1-01 mclr reset during normal operation 000h 000u uuuu ---0 1-uu mclr reset during sleep 000h 0001 0uuu ---0 1-uu wdt reset 000h 0000 1uuu ---0 1-uu wdt wake-up pc + 1 uuu0 0uuu ---0 u-uu brown-out reset 000h 0001 1uuu ---0 1-u0 interrupt wake-up from sleep, gie = 0 pc + 1 uuu1 0uuu ---u u-uu interrupt wake-up from sleep, gie = 1 0004h uuu1 0uuu ---u u-uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? . t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16c781/782 ds41171a-page 126 preliminary ? 2001 microchip technology inc. table 14-6: initialization condition for all registers register power-on reset or brown-out reset mclr reset or wdt reset wake-up via wdt or interrupt w (not a mapped register) xxxx xxxx uuuu uuuu uuuu uuuu indf 0000 0000 uuuu uuuu uuuu uuuu tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 pc + 1 (1) status 0001 1xxx 000q quuu (2) uuuq quuu (2) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta xxxx 0000 uuuu 0000 uuuu uuuu portb xxxx xx00 uuuu uu00 uuuu uu00 pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuqq pir1 0000 ---0 0000 ---0 0000 ---u calcon 000- ---- 000- ---- uuu- ---- tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con -000 0000 -uuu uuuu -uuu uuuu psmccon0 0000 0000 0000 0000 uuuu uuuu psmccon1 000- 0000 000- 0000 uuu- uuuu cm1con0 0000 0000 0000 0000 uuuu uuuu cm2con0 0000 0000 0000 0000 uuuu uuuu cm2con1 00-- ---0 00-- ---0 uu-- ---u opacon 00-- ---0 00-- ---0 uu-- ---u adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 0000 0000 0000 uuuu uuuu option_reg 1111 1111 1111 1111 uuuu uuuu trisa 1111 1111 1111 1111 uuuu uuuu trisb 1111 1111 1111 1111 uuuu uuuu pie1 0000 ---0 0000 ---0 uuuu ---u pcon ---0 1-qq ---0 1-uu ---u u-uu dac 0000 0000 0000 0000 uuuu uuuu dacon0 00-- --00 00-- --00 uu-- --uu wpub 1111 1111 1111 1111 uuuu uuuu iocb 1111 0000 1111 0000 uuuu uuuu refcon ---- 00-- ---- 00-- ---- uu-- lvdcon --00 0101 --00 0101 --uu uuuu ansel 1111 1111 1111 1111 uuuu uuuu adcon1 --00 ---- --00 ---- --uu ---- pmdatl xxxx xxxx uuuu uuuu uuuu uuuu pmadrl xxxx xxxx uuuu uuuu uuuu uuuu pmdath --xx xxxx --uu uuuu --uu uuuu pmadrh ---- xxxx ---- uuuu ---- uuuu pmcon1 1--- ---0 1--- ---0 1--- ---0 legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 2: see table 14-5 for reset value for specific condition.
? 2001 microchip technology inc. preliminary ds41171a-page 127 pic16c781/782 figure 14-8: time-out sequence on power-up (mclr not tied to v dd ) figure 14-9: slow v dd rise time (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 5v t pwrt t ost note 1: this time depends on the oscillator circuit used. (1)
pic16c781/782 ds41171a-page 128 preliminary ? 2001 microchip technology inc. 14.9 interrupts the devices have up to eight sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. when bit gie is enabled and an interrupt ? s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the ? return from interrupt ? instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables interrupts. the rb0/int/an4/v r pin interrupt, the rb port inter- rupt-on-change (iocb) and the tmr0 overflow inter- rupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function register pir1. the corresponding interrupt enable bits are contained in special function register pie1, and the peripheral interrupt enable bit is con- tained in special function register intcon. when an interrupt is serviced, the gie bit is cleared to disable any further interrupt. the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency is three or four instruction cycles. the exact latency depends on when the interrupt event occurs. the latency is the same for one or two-cycle instructions. individual inter- rupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 14.9.1 int interrupt external interrupt on rb0/int/an4/v r pin is edge trig- gered: either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can awaken the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the pro- cessor branches to the interrupt vector following a wake-up sequence. see section 14.12 for details on sleep mode. figure 14-10: interrupt logic note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the gie bit. c2if c2ie c1if c1ie adif adie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu peif lvdif lvdie
? 2001 microchip technology inc. preliminary ds41171a-page 129 pic16c781/782 14.9.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register sets the flag bit, t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit, t0ie (intcon<5>) (section 2.5). 14.9.3 portb interrupt-on-change (iocb) an input change on portb<7:0> sets flag bit rbif (intcon<0>). the portb pin(s) which can individu- ally generate interrupt are selectable in the iocb regis- ter. the interrupt can be enabled/disabled by setting/ clearing enable bit rbie (intcon<4>) (section 2.5). portb must be configured as a digital input. 14.10 context saving during interrupts during an interrupt, only the pc is saved on the stack. at minimum, w and status should be saved to pre- serve the context for the interrupted program. all regis- ters that may be corrupted by the interrupt service routine (isr), such as pclath or fsr, should be saved. example 14-1 stores and restores the status, w and pclath registers. the register, w_temp, is defined in common ram, the last 16 bytes of each bank that may be accessed from any bank. the status_temp and pclath_temp are defined in bank 0. the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register in bank 0. d) executes the isr code. e) restores the pclath register. f) restores the status register. g) restores w. example 14-1: saving status, w, and pclath registers #define w_temp 0x70 #define status_temp 0x71 #define pclath_temp 0x72 org 0x04 ; int vector movwf w_temp ; save w movf status,w movwf status_temp ; save status movf pclath,w movwf pclath_temp ; save pclath : (interrupt service routine) : movf pclath_temp,w movwf pclath movf status_temp,w movwf status swapf w_temp,f ; swapf loads w swapf w_temp,w ; w/o affect status retfie 14.11 watchdog timer (wdt) the watchdog timer uses a free running, on-chip rc oscillator, which does not require any external compo- nents. this oscillator is independent from the processor clock. the wdt runs even if the main clock of the device has been stopped (for example, by execution of a sleep instruction). during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status regis- ter is cleared upon a watchdog timer time-out. the wdt can be permanently enabled by program- ming the configuration bit wdte, or by software via the wdton bit in the power control register (pcon: 8eh). see section 14.8 and section 14.1. wdt time-out period values may be found in the elec- trical specifications. values for the wdt prescaler may be assigned using the option_reg register. note: the w_temp, status_temp and pclath_temp are defined in the com- mon ram area (70h - 7fh) to avoid regis- ter bank switching during context save and restore. note 1: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt. 2: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count is cleared, but the prescaler assignment is not changed.
pic16c781/782 ds41171a-page 130 preliminary ? 2001 microchip technology inc. figure 14-11: watchdog timer block diagram table 14-7: summary of watchdog timer registers from tmr0 clock source (figure 5-2) to tmr0 (figure 5-2) postscaler wdt timer wdte (2) 0 1 m u x psa (1) 8 - to - 1 mux ps<2:0> (1) 0 1 mux psa (1) wdt time-out note 1: psa and ps<2:0> are bits in the option_reg register. 8 2: wdte bit in the configuration word. wdton (3) 3: wdton bit in the pcon register. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) ? boden mclre pwrte wdte fosc2 fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 8eh pcon ? ? ? wdton ocsf ? bor por legend: shaded cells are not used by the watchdog timer. note 1: see register 14-1 for the full description of the configuration word bits.
? 2001 microchip technology inc. preliminary ds41171a-page 131 pic16c781/782 14.12 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer is cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode: place all i/o pins at either v dd , or v ss , ensure no external circuitry is drawing current from the i/o pin, power-down all peripherals, disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on- chip pull-ups on portb should be considered. 14.12.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, portb iocb, or any peripheral interrupts. external mclr reset causes a device reset. all other events are considered a continuation of program execu- tion and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. adc conversion (when adc clock source is rc). 3. programmable low voltage detect. 4. comparator c1 or c2 interrupt-on-change. 5. opa in comparator mode using iocb. other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction, then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 14.12.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction com- pletes as a nop . therefore, the wdt and wdt postscaler are not cleared, the to bit is not set, and pd bits are not cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device immedi- ately awakens from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler are cleared, the to bit is set, and the pd bit is cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c781/782 ds41171a-page 132 preliminary ? 2001 microchip technology inc. figure 14-12: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (3) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (1) pc+2 note 1: t ost = 1024t osc (drawing not to scale). this delay applies to lp, xt and hs modes only. 2: gie = ? 1 ? assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 3: clkout is not available in these osc modes, but shown here for timing reference.
? 2001 microchip technology inc. preliminary ds41171a-page 133 pic16c781/782 15.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxxx instruc- tion set summary in table 15-2 lists byte-oriented , bit- oriented , and literal and control operations. table 15- 1 shows the opcode field descriptions. for byte-oriented instructions, ? f ? represents a file reg- ister designator and ? d ? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the number of the file in which the bit is located. for literal and control operations, ? k ? represents an eight or eleven bit constant or literal value. table 15-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 s. table 15-2 lists the instructions recognized by the mpasm tm assembler. figure 15-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 15-1: general format for instructions a description of each instruction is available in the picmicro ? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compati- bility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c781/782 ds41171a-page 134 preliminary ? 2001 microchip technology inc. table 15-2: pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop .
? 2001 microchip technology inc. preliminary ds41171a-page 135 pic16c781/782 15.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal ? k ? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ? f ? . if ? d ? is 0, the result is stored in the w register. if ? d ? is 1, the result is stored back in reg- ister ? f ? . andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and ? ed with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit 'b' in register 'f' is set. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', the next instruction is executed. if bit 'b' is '1', then the next instruc- tion is discarded and a nop is exe- cuted instead, making this a 2t cy instruction.
pic16c781/782 ds41171a-page 136 preliminary ? 2001 microchip technology inc. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ? b ? in register ? f ? is ? 1 ? , the next instruction is executed. if bit ? b ? , in register ? f ? , is ? 0 ? , the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ? f ? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ? f ? are complemented. if ? d ? is 0, the result is stored in w. if ? d ? is 1, the result is stored back in register ? f ? . decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ? f ? . if ? d ? is 0, the result is stored in the w regis- ter. if ? d ? is 1, the result is stored back in register ? f ? .
? 2001 microchip technology inc. preliminary ds41171a-page 137 pic16c781/782 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ? f ? are decremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead, making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in regis- ter ? f ? . i f the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead, making it a 2t cy instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or ? ed with the eight-bit literal 'k'. the result is placed in the w reg- ister. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in regis- ter 'f'.
pic16c781/782 ds41171a-page 138 preliminary ? 2001 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ? k ? is loaded into w register. the don ? t cares will assemble as 0 ? s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to reg- ister 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. register f c
? 2001 microchip technology inc. preliminary ds41171a-page 139 pic16c781/782 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2 ? s complement method) from the eight-bit literal 'k'. the result is placed in the w register. register f c subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2 ? s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor ? ed with the eight-bit lit- eral 'k'. the result is placed in the w register.
pic16c781/782 ds41171a-page 140 preliminary ? 2001 microchip technology inc. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ? f ? . if ? d ? is 0, the result is stored in the w register. if ? d ? is 1, the result is stored back in register ? f ? .
? 2001 microchip technology inc. preliminary ds41171a-page 141 pic16c781/782 16.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian simulators - mplab sim software simulator emulators - mplab ice 2000 in-circuit emulator - icepic ? in-circuit emulator in-circuit debugger - mplab icd device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 16.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor a project manager customizable toolbar and key mapping a status bar on-line help the mplab ide allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro emulator and simulator tools (auto- matically updates all project information) debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 16.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all picmicro mcu ? s. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: integration into mplab ide projects. user-defined macros to streamline assembly code. conditional assembly for multi-purpose source files. directives that allow complete control over the assembly process. 16.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ? c ? compilers for microchip ? s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c781/782 ds41171a-page 142 preliminary ? 2001 microchip technology inc. 16.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: integration with mpasm assembler and mplab c17 and mplab c18 c compilers. allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: easier linking because single libraries can be included instead of many smaller files. helps keep code maintainable by grouping related modules together. allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 16.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 16.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 16.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 2001 microchip technology inc. preliminary ds41171a-page 143 pic16c781/782 16.8 mplab icd in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash picmicro mcus and can be used to develop for this and other picmicro microcontrollers. the mplab icd utilizes the in-circuit debugging capa- bility built into the flash devices. this feature, along with microchip ? s in-circuit serial programming tm proto- col, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watch- ing variables, single-stepping and setting break points. running at full speed enables testing hardware in real- time. 16.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program picmicro devices. it can also set code protection in this mode. 16.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all picmicro devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 16.11 picdem 1 low cost picmicro demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip ? s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 16.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c781/782 ds41171a-page 144 preliminary ? 2001 microchip technology inc. 16.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 16.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 16.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip ? s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 2001 microchip technology inc. preliminary ds41171a-page 145 pic16c781/782 table 16-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 c compiler mplab ? c18 c compiler mpasm tm assembler/ mplink tm object linker emulators mplab ? ice in-circuit emulator ** icepic tm in-circuit emulator debugger mplab ? icd in-circuit debugger * * programmers picstart ? plus entry level development programmer ** pro mate ? ii universal device programmer ** demo boards and eval kits picdem tm 1 demonstration board ? picdem tm 2 demonstration board ? ? picdem tm 3 demonstration board picdem tm 14a demonstration board picdem tm 17 demonstration board k ee l oq ? evaluation kit k ee l oq ? transponder kit microid tm programmer ? s kit 125 khz microid tm developer ? s kit 125 khz anticollision microid tm developer ? s kit 13.56 mhz anticollision microid tm developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c781/782 ds41171a-page 146 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 147 pic16c781/782 17.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ...... -55 c to +125 c storage temperature ............................................................................................................ ............. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr and ra4) ................................... -0.3v to (v dd + 0.3 v) voltage on v dd with respect to v ss .......................................................................................................-0.3 to +7.5 v maximum voltage between av dd and v dd pins............................................................................................... 0.3 v maximum voltage between av ss and v ss pins ............................................................................................... 0.3 v voltage on mclr with respect to v ss ................................................................................................ -0.3 v to +8.5 v voltage on ra4 with respect to vss ............................................................................................. ......0.3 v to +10.5 v total power dissipation (1) (pdip, soic)............................................................................................................. 1.0 w total power dissipation (1) (ssop) .................................................................................................................... 0.65 w maximum current out of v ss pin ..................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................ 250 ma input clamp current, i ik (v i < 0 or v i > v dd .................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ............................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma maximum current sunk by porta and portb (combined)........................................................................... 20 0 ma maximum current sourced by porta and portb (combined....................................................................... 200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v ol x i ol ). ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c781/782 ds41171a-page 148 preliminary ? 2001 microchip technology inc. figure 17-1: pic16c781/782 voltage-frequency graph, -40 c t a +85 c figure 17-2: pic16lc781/782 voltage-frequency graph, -40 c t a +85 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 0410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 5.5 4.0 2.7 4.5-
? 2001 microchip technology inc. preliminary ds41171a-page 149 pic16c781/782 17.1 dc characteristics: power supply table 17-1: dc characteristics: pic16c781/782, pic16lc781/782 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature-40 c t a +85 c for industrial param no. sym characteristic min typ ? max units conditions d001 v dd supply voltage 4.0 4.5 ? ? 5.5 5.5 v ? xt, ec, rc, intrc oscillator hs oscillator d001a v dd supply voltage (pic16lc781/782) 2.7 4.5 ? ? 5.5 5.5 v v xt, ec, rc, intrc oscillator hs oscillator d002* v dr ram data retention voltage (1) ? 1.5 ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? tbd ? v see section on power-on reset for details d004* sv dd v dd rise rate to ensure internal power-on reset signal 0.05 ?? v/ms see section on power-on reset for details. pwrt enabled d010 i dd supply current (2) ? ? ? ? tbd tbd tbd tbd tbd tbd tbd tbd ma ma ma ma f osc = 20 mhz, v dd = 5.5v* hs oscillator f osc = 20 mhz, v dd = 4.5v hs oscillator f osc = 4 mhz, v dd = 4.0v* xt, rc w/clkout f osc = 32 khz, v dd = 4.0v lp oscillator d020 d020a i pd power-down current (3) ? ? tbd 1.5 tbd 19 a a v dd = 5.5v v dd = 4.0v i opa operational amplifier ? tbd tbd tbd tbd ma ma v dd = 5.0v, gbwp = 0 v dd = 5.0v, gbwp = 1 i vc * voltage comparators c1 and c2 ? ? tbd tbd tbd tbd ma ma v dd = 5.0v, v id >100 mv c1sp = 0 v dd = 5.0 , v id >100 mv c1sp = 1 i adc * digital to analog converter (dac) ? tbd tbd ma v dd = 5.0v d021 i wdt * watchdog timer ? tbd tbd ma v dd = 4.0v d026 i ad * analog-to-digital converter (adc) ? tbd tbd ma v dd = 5.5v, adc not converting i plvd * programmable low voltage detect tbd tbd ma v dd = 4.0v i pbor * programmable brown-out reset tbd tbd ma v dd = 5.0v 1a f osc lp oscillator, operating freq. intrc oscillator operating freq. xt oscillator operating freq. hs oscillator operating freq. 9 ? ? 0 0 ? 4 37 ? ? 200 ? ? 4 20 khz mhz khz mhz mhz all temperatures all temperatures, oscf = 1 all temperatures, oscf = 0 all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins configured as inputs, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins configured as iputs and tied to v dd or v ss .
pic16c781/782 ds41171a-page 150 preliminary ? 2001 microchip technology inc. 17.2 dc characteristics: input/output pins table 17-2: dc characteristics: pic16c781/782, pic16lc781/782 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial and operating voltage v dd range as described in dc spec section 17-1 param no. sym characteristic min typ ? max units conditions input low voltage v il i/o ports: d030 with ttl buffer v ss ? 0.15v dd v for entire v dd range d030a v ss ? 0.8v v 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss ? 0.2v dd v for entire v dd range d032 mclr v ss ? 0.2v dd v d033 osc1 (in xt, hs, lp and ec) v ss ? 0.3 v d v input high voltage v ih i/o ports: ? d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a (0.25v dd + 0.8v) ? v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd ? v dd v for entire v dd range d042 mclr 0.8v dd ? v dd v d042a osc1 (xt, hs, lp and ec) 0.7v dd ? v dd v d070 i purb portb weak pull-up current per pin 50 250 400 a v dd = 5v, v pin = v ss input leakage current (1,2) d060 i il i/o ports (with digital functions) ?? 1 a vss v pin v dd , pin at hi-impedance d060a i il i/o ports (with analog functions) ?? 100 na vss v pin v dd , pin at hi-impedance d061 ra5/mclr /v pp ?? 5 a vss v pin v dd d063 osc1 ?? 5 a vss v pin v dd , xt, hs, lp and ec osc configuration output low voltage d080 v ol i/o ports (includes clkout) ?? 0.6 v i ol = 8.5 ma, v dd = 4.5v output high voltage d090 v oh i/o ports (2) (includes clkout) v dd - 0.7 ?? vi oh = -3.0 ma, v dd = 4.5v d150* v od open drain high voltage ?? 10.5 v ra4 pin capacitive loading specs on output pins* d100 cosc2 osc2 pin ?? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) ?? 50 pf * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 2: negative current is defined as current sourced by the pin.
? 2001 microchip technology inc. preliminary ds41171a-page 151 pic16c781/782 17.3 ac characteristics: pic16c781/782 (industrial) 17.3.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 17-3: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp osc osc1 ck clkout dt data in t0 t0cki io i/o port t1 t1cki mc mclr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance high high low low v dd /2 cl rl pin pin v ss v ss cl rl = 464 ? cl = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c781/782 ds41171a-page 152 preliminary ? 2001 microchip technology inc. 17.3.2 timing diagrams and specifications figure 17-4: clkout and i/o timing table 17-3: clkout and i/o timing requirements note 1: refer to figure 17-3 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value parameter no. sym characteristic min typ ? max units conditions 10* t os h2 ck losc1 to clkout ? 75 200 ns (note 1) 11* t os h2 ck hosc1 to clkout ? 75 200 ns (note 1) 12* t ck r clkout rise time ? 35 100 ns (note 1) 13* t c kf clkout fall time ? 35 100 ns (note 1) 14* t ck l2 io vclkout to port out valid ?? 0.5t cy + 20 ns (note 1) 15* t io v2 ck h port in valid before clkout 0.25t cy + 25 ?? ns (note 1) 16* t ck h2 io l port in hold after clkout 0 ?? ns (note 1) 17* t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18* t os h2 io losc1 (q2 cycle) to port input invalid (i/o in hold time) pic16 c 781/782 100 ?? ns pic16 lc 781/782 200 ?? ns 19* t io v2 os h port input valid to osc1 (i/o in setup time) 0 ?? ns 20* t io r port output rise time pic16 c 781/782 ? 10 25 ns pic16 lc 781/782 ?? 60 ns 21* t io f port output fall time pic16 c 781/782 ? 10 25 ns pic16 lc 781/782 ?? 60 ns 22 ?? *t inp int pin high or low time t cy ?? ns 23 ?? *t rbp rb7:rb0 change int high or low time t cy ?? ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc .
? 2001 microchip technology inc. preliminary ds41171a-page 153 pic16c781/782 figure 17-5: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 17-4: external clock timing requirements parameter no. sym characteristic min typ ? max units conditions 1a f osc external clkin frequency (1) dc ? 4 mhz xt osc mode dc ? 20 mhz ec osc mode dc ? 20 mhz hs osc mode dc ? 200 khz lp osc mode oscillator frequency (1) 0.1 ? 4 mhz xt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1t osc external clkin period (1) 250 ?? ns xt and rc osc mode 50 ?? ns ec osc mode 50 ?? ns hs osc mode 5 ?? slp osc mode oscillator period (1) 250 ? 10,000 ns xt osc mode 50 ? 250 ns hs osc mode 5 ?? slp osc mode 2t cy instruction cycle time (1) 200 t cy dc ns tcy = 4/fosc 3* t osl , t osh external clock in (osc1) high or low time 100 ?? ns xt oscillator 2.5 ?? s lp oscillator 15 ?? ns hs oscillator ec oscillator 4* t osr , t osf external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ?? 15 ns hs oscillator ec oscillator * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c781/782 ds41171a-page 154 preliminary ? 2001 microchip technology inc. table 17-5: internal rc oscillator calibrated frequencies pic16c781/782, pic16lc781/782 figure 17-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 17-7: brown-out reset timing ac characteristics standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c (industrial) operating voltage v dd range is described in section 17-1. parameter no. sym characteristic min typ (1) max units conditions internal calibrated rc frequency 3.65 4.00 4.28 mhz v dd = 5.0v internal calibrated rc frequency 3.55* 4.00 4.31* mhz v dd = 2.5v * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note 1: refer to figure 17-3 for load conditions. v dd bv dd 35
? 2001 microchip technology inc. preliminary ds41171a-page 155 pic16c781/782 table 17-6: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements figure 17-8: brown-out reset characteristics parameter no. sym characteristic min typ ? max units conditions 30* t mcl mclr pulse width (low) 2 ?? sv dd = 5v, -40 c to +85 c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40 c to +85 c 32* t ost oscillation start-up timer period ? 1024 t osc ?? t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40 c to +85 c 34* t ioz i/o hi-impedance from mclr low or watchdog timer reset ?? 2.1 s 35* t bor brown-out reset pulse width 100 ?? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v bor reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) 72 ms time out (1) note 1: only if power-up timer is enabled. if timer is disabled, time-out is 0 ms
pic16c781/782 ds41171a-page 156 preliminary ? 2001 microchip technology inc. figure 17-9: timer0 and timer1 external clock timings note: refer to figure 17-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki ra6/osc2/clkout/t1cki tmr0 or tmr1
? 2001 microchip technology inc. preliminary ds41171a-page 157 pic16c781/782 table 17-7: timer0 and timer1 external clock requirements param no. sym characteristic min typ ? max units conditions 40* t toh t0cki high pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 41* t tol t0cki low pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 42* t top t0cki period no prescaler t cy + 40 ?? ns with prescaler greater of: 20 or t cy + 40 n ?? ns n = prescale value (2, 4, ..., 256) 45* t t 1 h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 781/782 15 ?? ns asynchronous pic16 c 781/782 30 ?? ns 45* t t 1 h t1cki high time synchronous, prescaler = 1 0.5tcy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 lc 781/782 15 ?? ns asynchronous pic16 lc 781/782 30 ?? ns 46* t t 1 l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 781/782 15 ?? ns asynchronous pic16 c 781/782 30 ?? ns 46* t t 1 l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 lc 781/782 15 ?? ns asynchronous pic16 lc 781/782 30 ?? ns 47* t t 1 p t1cki input period synchronous pic16 c 781/782 greater of: 30 or t cy + 40 n ?? ns n = prescale value (1, 2, 4, 8) asynchronous pic16 c 781/782 60 ?? ns 47* t t 1 p t1cki input period synchronous pic16 lc 781/782 greater of: 30 or t cy + 40 n ?? ns n = prescale value (1, 2, 4, 8) asynchronous pic16 c 781/782 60 ?? ns f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 50 khz 48* tcke2tmrl delay from external clock edge to timer increment 2t osc ? 7t osc ? * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c781/782 ds41171a-page 158 preliminary ? 2001 microchip technology inc. 17.4 operational amplifier table 17-8: dc characteristics: operational amplifier (opa) dc characteristics standard operating conditions (unless otherwise stated): v dd = 2.7v to 5.5v, t a = 25 c, v cm = v dd /2, r l = 100 k ? to v dd /2, and v out ~ v dd /2 operating temperature -40 c to +85 c for industrial param no. parameters symbol min typ max units conditions input offset voltage input offset voltage v os tbd 2 tbd mv prior to auto calibration input offset voltage input offset voltage v os tbd 100 tbd v following auto calibration input current and impedance input bias current input offset bias current i b i os -50 ? ? 1 +50 ? na pa following auto calibration common mode common mode input range common mode rejection v cm cmr v ss tbd ? 80 v dd -1.4 ? v db following auto calibration v dd = 5 v v cm = v dd /2, frequency = dc open loop gain dc open loop gain dc open loop gain dc open loop gain dc open loop gain a ol a ol ? ? 90 80 ? ? db db gbwp = 1 following auto calibration r l = 25 k ? connected to v dd /2, 50 mv < v out < v dd - 50 mv r l = 5 k ? connected to v dd /2, 100 mv < v out < v dd - 100 mv a ol a ol ? ? tbd tbd ? ? db db gbwp = 0 following auto calibration rl = 50 k ? connected to v dd /2, 50 mv < v out < v dd - 50 mv rl = 100 k ? connected to v dd /2, 50 mv < v out < v dd - 50 mv output output voltage swing output short circuit current v out i sc v ss +0.1 ? ? 25 v dd -0.1 tbd v ma gbwp = 1 following auto calibration r l = 5 k ? connected to v dd /2 v dd = 5 v power supply power supply rejection psr ? 80 ? db following auto calibration auto calibration reference acr tbd 1.2 tbd v calref = 0
? 2001 microchip technology inc. preliminary ds41171a-page 159 pic16c781/782 table 17-9: ac characteristics: operational amplifier (opa) ac characteristics standard operating conditions (unless otherwise stated): v dd = 2.7v to 5.5v, v ss = gnd, t a = 25 c, vcm = v dd /2, rl = 100k ? to v dd /2, and v out = v dd /2 operating temperature -40 c to +85 c for industrial param no. parameters symbol min typ max units conditions gain bandwidth product gbwp gbwp ? ? 75 2 ? ? khz mhz v dd = 5v, gbwp = 0 v dd = 5v, gbwp = 1 input offset auto calibration time turn on time t z t z t on t on ? ? ? ? 300 tbd 10 tbd tbd tbd tbd tbd s s s s v dd = 5v, gbwp = 1 v dd = 5v gbwp = 0 v dd = 5v, gwbp = 1 v dd = 5v, gbwp = 0 phase margin m m ? ? tbd tbd ? ? degrees degrees v dd = 5v, gbwp = 0 v dd = 5v, gbwp = 1 slew rate sr sr ? ? tbd tbd ? ? v/ s v/ s v dd = 5v, gbwp = 0 v dd = 5v, gbwp = 1 note: data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c781/782 ds41171a-page 160 preliminary ? 2001 microchip technology inc. 17.5 comparators table 17-10: dc characteristics: voltage comparators c1 and c2 table 17-11: ac characteristics: comparators c1 and c2 dc characteristics standard operating conditions (unless otherwise stated): v dd = 2.7v to 5.5v, t a = 25 c, v cm = v dd /2 operating temperature -40 c to +85 c for industrial param no. parameters symbol min typ max units conditions input offset voltage v os tbd tbd 1 2.5 tbd tbd mv mv c1sp = 1, c2sp = 1 c1sp = 0, c2sp = 0 input current and impedance input bias current input offset bias current i b i os tbd ? ? tbd ? tbd na na common mode common mode input range common mode rejection v cm cmr v ss ? ? 70 v dd - 1.4v v db v dd = 5v v cm = v dd /2, frequency = dc open loop gain dc open loop gain a ol ? 90 ? db power supply rejection psr ? tbd ? db v dd = 5v ac characteristics standard operating conditions (unless otherwise stated): v dd = 2.7v to 5.5v, t a = 25 c, v cm = v dd /2 operating temperature -40 c to +85 c for industrial param no. parameters symbol min typ max units conditions response time response time t r t r t r t r ? ? ? ? 75 0.5 100 0.5 ? ? tbd tbd ns s ns s v dd = 5v, c1sp = 1, c2sp = 1, comparator output signal is for internal use only, input overdrive = 10 mv, step = 110 mv, v cm = v dd /2. v dd = 5v, c1sp = 0, c2sp = 0, comparator output signal is for internal use only, input overdrive = 10 mv, step = 110 mv, v cm = v dd /2. v dd = 5 , c l = 100 pf, c1sp = 1, c2sp = 1, comparator output is available on i/o pin, input overdrive = 10 mv, step = 110 mv, v cm = v dd /2. v dd = 5 , c l = 100 pf, c1sp = 0, c2sp = 0, comparator output is available on i/o pin, input overdrive = 10 mv, step = 110 mv, v cm = v dd /2. turn on time t on ? ? 10 tbd tbd tbd s s c1sp = 0, c2sp = 0, v dd = 5v c1sp = 1, c2sp = 1, v dd = 5v
? 2001 microchip technology inc. preliminary ds41171a-page 161 pic16c781/782 17.6 digital-to-analog converter (dac) table 17-12: dc characteristics: digital-to-analog converter (dac) table 17-13: ac characteristics: digital-to-analog converter (dac) dc characteristics standard operating conditions (unless otherwise stated): v dd = 2.7v to 5.5v, t a = 25 c v dd = 5v, dacref = 5v operating temperature -40 c to +85 c for industrial param no. parameters symbol min typ max units conditions resolution res 8 bits transfer function accuracy integral non-linearity error differential non-linearity error offset error gain error inl (1) dnl (1) tbd tbd tbd tbd .25 .10 2.5 .25 tbd tbd tbd tbd lsb lsb mv lsb v dd = 5v, dacref = 5v dacref input characteristics dacref input impedance dacref input max voltage r ref v max tbd tbd 100 ? ? v dd k ? v output characteristics output voltage range output short circuit current output series resistance v out v ss +.05 v ss +0.1 ? ? v dd - 0.05 v dd -0.1 v v v dd = 5v r l = 100 k ? to v dd /2 v dd = 5v r l = 25 k ? to v dd /2 i sc * ? 2tbdmav dd = 5v r o * ? ? tbd tbd ? v dd 3v v dac = v dd /2 power supply power supply current i dac ? 250 tbd av dd = 5v * characterized, but not tested. note 1: calculated using end point method. ac characteristics standard operating conditions (unless otherwise stated): v dd = 2.7 v to 5.5 v, ta = 25 c operating temperature-40 c to +85 c for industrial param no. parameters symbol min typ max units conditions output characteristics slew rate settling time turn on time sr t s t on ? ? ? 1 5 10 ? 10 tbd v/ s s s v dd = 5 v, c l = 50 pf v dd = 5 v, c l = 50 pf settling time to 1/2 lsb for 10%fs to 90%fs step v dd = 5 v note 1: data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c781/782 ds41171a-page 162 preliminary ? 2001 microchip technology inc. 17.7 analog peripherals characteristics 17.7.1 bandgap voltage bandgap voltage is used as the reference voltage in the pbor, plvd, auto calibration, and vr modules figure 17-10: bandgap start-up time table 17-14: bandgap start-up time 17.7.2 vr module table 17-15: dc characteristics: vr v bgap = 1.32v v bgap enable bandgap bandgap stable t bgap (internal use only) parameter no. sym characteristic min typ ? max units conditions 36* t bgap bandgap start-up time ? 30 ? s defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. dc characteristics standard operating conditions (unless otherwise stated): operating temperature -40 c t a +85 c for industrial operating voltage v dd as described in section 17.1 param no. symbol characteristic min typ ? max units conditions d400 v r output voltage ? 3.072 ? vv dd 3.5v d402* tcv out output voltage temperature coefficient ? tbd tbd ppm/ c d404* i vrefso external load source ?? 5ma d405* i vrefsi external load sink ?? -5 ma c l * external capacitor load ?? 200 pf d406* dv out / di out load regulation ? 1tbd mv/ma i source = 0 ma to 5 ma ? 1tbd i sink = 0 ma to 5 ma d407* dv out / dv dd supply regulation ?? 1mv/v * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2001 microchip technology inc. preliminary ds41171a-page 163 pic16c781/782 17.7.3 programmable low voltage detect module (plvd) table 17-16: low voltage detect characteristics table 17-17: electrical characteristics: plvd v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software anytime during the gray area) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial operating voltage v dd range as described in dc spec section 17-1. param no. characteristic symbol min typ ? max units conditions d420* p lvd voltage lv = 0100 v plvd 2.35 ? 2.80 v ? lv = 0101 2.55 ? 3.02 v ? lv = 0110 2.64 ? 3.14 v ? lv = 0111 2.83 ? 3.37 v ? lv = 1000 3.11 ? 3.71 v ? lv = 1001 3.29 ? 3.93 v ? lv = 1010 3.39 ? 4.04 v ? lv = 1011 3.58 ? 4.26 v ? lv = 1100 3.77 ? 4.49 v ? lv = 1101 3.95 ? 4.71 v ? lv = 1110 4.23 ? 5.05 v ? ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: production tested at t amb = 25 c. specifications over temperature limits ensured by characterization.
pic16c781/782 ds41171a-page 164 preliminary ? 2001 microchip technology inc. 17.7.4 programmable brown-out reset module dc characteristics: pbor table 17-18: adc converter characteristics pic16c781/782 dc characteristics standard operating conditions (unless otherwise stated): operating temperature-40 c t a +85 c for industrial operating voltage v dd range as described in dc spec section 17-1. param no. characteristic symbol min typ max units conditions d005* bor voltage borv<1:0> = 11 v bor 2.35 ? 2.80 v ? borv<1:0> = 10 2.55 ? 3.02 ? borv<1:0> = 01 3.95 ? 4.71 ? borv<1:0> = 00 4.23 ? 5.05 ? param no. sym characteristic min typ ? max units conditions a01 n r resolution ?? 8 bits adc ref = av dd = 5.12v, v ss v ain adc ref a02 e abs absolute error ?? < 1 lsb adc ref = av dd = 5.12v, v ss v ain adc ref ?? < 2 lsb adc ref = av dd = 3.0v (3) a03 i nl integral now linearity error ?? < 1 lsb adc ref = av dd = 5.12v, v ss v ain adc ref ?? < 2 lsb adc ref = av dd = 3.0v (3) a04 d nl differential now linearity error ?? < 1 lsb adc ref = av dd = 5.12v, v ss v ain adc ref ?? < 2 lsb adc ref = av dd = 3.0v (3) a05 g n gain error ?? < 1 lsb adcref = av dd = 5.12v, v ss v ain adc ref ?? < 2 lsb adc ref = av dd = 3.0v (3) a06 e off offset error ?? < 1 lsb adc ref = av dd = 5.12v, v ss v ain adc ref ?? < 2 lsb adc ref = av dd = 3.0v (3) a10 ? monotonicity ? guaranteed (4) ?? v ss v ain adc ref a20 adc ref reference voltage 3.0v ? v dd + 0.3 v ? a25 v ain analog input voltage v ss - 0.3 ? adc ref v ? a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? ? a40 i adc adc conversion current (v dd ) ? 180 ? a average current consumption when adc is on. (1) a50 i ref adc ref input current (2) 10 ? ? ? 1000 40 a a during v ain acquisition. based on differential of v hold to v ain . to charge c hold , see section 9.3. during adc conversion cycle. * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when adc is off, it will not consume any current other than minor leakage current. the power-down current specification (d020a) includes any such leakage from the adc module. 2: adc ref current is from ra3/an3/v ref 1 pin or av dd pin, whichever is selected as reference input. 3: these specifications apply if adc ref = 3.0 v and if av dd 3.0 v. v ain must be between v ss and adc ref . 4: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
? 2001 microchip technology inc. preliminary ds41171a-page 165 pic16c781/782 figure 17-11: adc conversion timing table 17-19: adc conversion requirements 131 130 132 bsf adcon0, go q4 adc clk adc data adres adif go/done sample old_data sampling stopped conversion new_data (t osc /2) (1) 7 6 5432 10 note 1: if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. 1 t cy complete param no. sym characteristic min typ ? max units conditions 130 t ad adc clock period adc internal rc oscillator period pic16c781/782 pic16lc781/782 2.0 tbd 4.0 tbd 6.0 tbd s s adc rc mode 131 t cnv conversion time (not including s/h time) (1) ? 9.5 ? t ad 132 t acq acquisition time (2) 5* 20 ? ? ? s s the minimum time is the ampli- fier settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 19.5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to adc clock start ? t osc /2 ? ? if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert sample time 1.5 ? ? t ad * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these specifications ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min. conditions.
pic16c781/782 ds41171a-page 166 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 167 pic16c781/782 18.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. in some graphs or tables the data presented is outside specified operating range (e.g., outside specified v dd range.). this is for information only and devices are ensured to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. standard deviation is denoted by sigma ( ). typ or typical represents the mean of the distribution at 25 c. max or maximum represents the mean +3 over the temperature range of -40 c to 85 c. min or minimum represents the mean -3 over the tem- perature range of -40 c to 85 c. graphs and tables are not available at this time.
pic16c781/782 ds41171a-page 168 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 169 pic16c781/782 19.0 packaging information 19.1 package marking information yywwnnn xxxxxxxxxxx xxxxxxxxxxx 20-lead ssop example xxxxxxxx yywwnnn 20-lead cerdip windowed pic16c781 example 0105017 xxxxxxxx 20-lead soic xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxx example 20-lead pdip xxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxx pic16c781-i/p 0110017 0107017 -i/ss pic16c781 /jw xxxxxxxxxxxxxx example 0110017 pic16c781/so legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic16c781/782 ds41171a-page 170 preliminary ? 2001 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic
? 2001 microchip technology inc. preliminary ds41171a-page 171 pic16c781/782 20-lead cerdip windowed diagram not available at this time.
pic16c781/782 ds41171a-page 172 preliminary ? 2001 microchip technology inc. 20-lead plastic small outline (so) ? wide, 300 mil (soic) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-094 foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 13.00 12.80 12.60 .512 .504 .496 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units h l c 45 1 2 d p n b e e1 a2 a a1 significant characteristic
? 2001 microchip technology inc. preliminary ds41171a-page 173 pic16c781/782 20-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.65 1.52 1.40 .065 .060 .055 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.56 3.30 3.05 .140 .130 .120 l tip to seating plane 26.42 26.24 26.04 1.040 1.033 1.025 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.87 7.49 .325 .310 .295 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-019 significant characteristic
pic16c781/782 ds41171a-page 174 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page 175 pic16c781/782 index a adc accuracy/error ............................................................ 75 connection considerations......................................... 76 conversion time ......................................................... 75 converter characteristics ......................................... 164 effects of a reset ..................................................... 76 faster conversion - lower resolution trade-off ........ 75 flow chart of adc operation ..................................... 77 references.................................................................. 76 transfer function ........................................................ 76 adc acquisition requirements........................................... 73 adc conversion clock ....................................................... 72 adc minimum charging time ............................................ 73 adc operation during sleep ........................................... 75 analog signal multiplexing diagram ..................................... 7 analog-to-digital converter (adc) module ......................... 69 analog-to-digital converter module control registers ........................................................ 70 assembler mpasm assembler ................................................... 141 b banking, data memory ....................................................... 17 block diagrams adc module................................................................ 69 auto calibration module.............................................. 85 comparator c1 simplified........................................... 90 comparator c2 simplified........................................... 90 dac converter............................................................ 80 low voltage detect ..................................................... 64 on-chip reset circuit ............................................... 121 opa module................................................................ 83 pic16c781 ................................................................... 5 PIC16C782 ................................................................... 6 psmc module in dual alternating output pwm mode ............................................................... 100 psmc module in single output psm mode ............. 102 psmc module in single output pwm mode .............. 99 ra0/an0/opa+ pin .................................................... 27 ra1/an1/opa- pin ..................................................... 28 ra2/an2/vref2 pin .................................................. 29 ra3/an3/vref1 pin .................................................. 30 ra4/t0cki pin............................................................ 31 ra5/mclr /vpp.......................................................... 32 ra6/osc2/clkout/t1cki pin ................................. 33 ra7/osc1/clkin pin ................................................ 34 rb0/int/an4/vr pin .................................................. 37 rb1/an5/vdac pin.................................................... 38 rb2/an6 pin............................................................... 39 rb3/an7/opa pin ...................................................... 40 rb4 pin....................................................................... 41 rb5 pin....................................................................... 42 rb6/c1/psmc1a pin ................................................. 43 rb7/c2/psmc1b/t1g pin ......................................... 44 rc oscillator mode................................................... 120 timer0 ......................................................................... 51 timer0/wdt prescaler................................................ 53 timer1....................................................................... 58 watchdog timer (wdt) ............................................ 130 boost lc switching power supply.................................... 107 bor dc characteristics.................................................... 164 bor. see brown-out reset brown-out reset (bor).................................... 117, 125, 126 buck configuration lc power supply............................... 112 buck lc switching power supply..................................... 110 c c1 input to psmc w/dac as reference ............................ 95 c2 configuration program .................................................. 95 calcon register .............................................................. 84 calculating the minimum required acquisition time ................................................................. 73 clock noise......................................................................... 76 code examples doing an adc conversion ......................................... 74 code protection ................................................................ 117 comparator c1 control register ........................................ 89 comparator c2 configuration with output synchronized to t1cki....................................................... 95 comparator c2 control registers ...................................... 92 comparator c2 synchronized to t1cki ............................. 95 comparator configuration .................................................. 95 comparator module ............................................................ 89 associated registers.................................................. 98 control registers........................................................ 89 effects of a reset..................................................... 98 output state versus input conditions......................... 89 configuration as opamp or comparator ........................... 86 configuration bits ............................................................. 117 configuration of comparator c1 with dac......................... 96 configuring the adc module .............................................. 72 configuring the reference voltages................................... 72 control register cm2con0 ............................................... 92 control register t1con..................................................... 56 d dac configuration.............................................................. 81 dac module accuracy/error............................................................ 81 associated registers/bits........................................... 81 dac transfer function ............................................... 81 differential non-linearity error ................................... 81 effects of a reset..................................................... 81 gain error ................................................................... 81 integral non-linearity error ........................................ 81 monotonicity ............................................................... 81 offset error ................................................................. 81 data memory bank select (rp bits) ................................................. 17 data memory organization................................................. 11 register file map ....................................................... 12 dc characteristics pic16c781/782, pic16lc781/782 (industrial)......................................................... 149 development support ....................................................... 141 device overview................................................................... 5 digital-to-analog converter (dac) module......................... 79 control registers........................................................ 79 direct addressing ............................................................... 24
pic16c781/782 ds41171a-page 176 preliminary ? 2001 microchip technology inc. e ec mode ........................................................................... 119 effect of reset on core registers .................................... 24 summary..................................................................... 24 effects of reset ................................................................ 52 electrical characteristics................................................... 147 errata .................................................................................... 3 examples dac configuration ...................................................... 81 opamp calibration mode configuration..................... 86 peripheral configuration ........................................... 113 psmc configuration ................................................. 109 psmc configuration example for a buck mode switching power supply ................................. 111 window comparator ................................................... 97 external power-on reset circuit ....................................... 122 f firmware instructions........................................................ 133 fsr register....................................................................... 15 g general purpose register file............................................ 13 i i/o port analog/digital mode............................................... 25 i/o ports .............................................................................. 25 icepic in-circuit emulator ............................................... 142 id locations ...................................................................... 117 in-circuit serial programming (icsp) ............................... 117 indirect addressing ............................................................. 24 initialization condition for all registers............................. 126 initializing timer0 ................................................................ 51 instruction format ............................................................. 133 instruction set ................................................................... 133 addlw ..................................................................... 135 addwf ..................................................................... 135 andlw ..................................................................... 135 andwf ..................................................................... 135 bcf ........................................................................... 135 bsf ........................................................................... 135 btfsc ...................................................................... 136 btfss ...................................................................... 135 call ......................................................................... 136 clrf......................................................................... 136 clrw........................................................................ 136 clrwdt................................................................... 136 comf ....................................................................... 136 decf ........................................................................ 136 decfsz.................................................................... 137 goto........................................................................ 137 incf.......................................................................... 137 incfsz ..................................................................... 137 iorlw....................................................................... 137 iorwf ...................................................................... 137 movf........................................................................ 138 movlw..................................................................... 138 movwf .................................................................... 138 nop .......................................................................... 138 retfie ..................................................................... 138 retlw...................................................................... 138 return ................................................................... 138 rlf ........................................................................... 138 rrf........................................................................... 139 sleep ...................................................................... 139 sublw ..................................................................... 139 subwf..................................................................... 139 swapf ..................................................................... 139 xorlw..................................................................... 139 xorwf .................................................................... 140 int interrupt (rb0/int/an4/vr). see interrupt sources intcon register gie bit ........................................................................ 19 inte bit ...................................................................... 19 intf bit ...................................................................... 19 peie bit ...................................................................... 19 rbie bit ...................................................................... 19 rbif bit ...................................................................... 19 t0ie bit ....................................................................... 19 t0if bit ....................................................................... 19 interrupt sources ...................................................... 117, 128 rb0/int pin, external............................................... 128 tmr0 overflow................................................... 52, 129 interrupts, context saving during..................................... 129 interrupts, enable bits global interrupt enable (gie bit) .............................. 128 interrupt-on-change (rb7:rb0) enable (rbie bit).................................................................. 129 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) .................................................................. 129 tmr0 overflow flag (t0if bit)................................. 129 k k ee l oq evaluation and programming tools .................... 144 l low power window comparator with interrupt .................. 96 low voltage detect associated register summary ................................... 67 low voltage detect registers ............................................ 67 low voltage detect waveforms ......................................... 65 lp, xt and hs modes ...................................................... 119 m master clear (mclr ) mclr reset, normal operation....................... 125, 126 mclr reset, sleep................................ 121, 125, 126 memory organization ......................................................... 11 mplab c17 and mplab c18 c compilers ..................... 141 mplab icd in-circuit debugger ...................................... 143 mplab ice high performance universal in-circuit emulator with mplab ide ................................ 142 mplab integrated development environment software ...................................................... 141 mplink object linker/mplib object librarian ................ 142 o opa auto calibration.......................................................... 83 opa module associated registers .................................................. 87 common mode voltage range................................... 86 effects of a reset..................................................... 86 gain bandwidth product ............................................. 86 input offset voltage .................................................... 86 leakage current ......................................................... 86 open loop gain ......................................................... 86 opa offset voltage ............................................................ 84 opcode field descriptions............................................. 133 operational amplifier (opa) module .................................. 83
? 2001 microchip technology inc. preliminary ds41171a-page 177 pic16c781/782 option_reg register intedg bit ................................................................. 18 ps bits .................................................................. 18, 52 psa bit.................................................................. 18, 52 rbpu bit..................................................................... 18 t0cs bit................................................................ 18, 51 t0se bit................................................................ 18, 51 oscillator configuration..................................................... 119 clkout ................................................................... 120 dual speed operation for intrc modes.................. 120 ec ..................................................................... 119, 123 er ............................................................................. 119 hs ..................................................................... 119, 123 intrc ............................................................... 119, 123 lp...................................................................... 119, 123 xt ..................................................................... 119, 123 oscillator, wdt ................................................................. 129 oscillators rc, block diagram ................................................... 120 otp program memory read .............................................. 49 p package marking information ........................................... 169 paging, program memory ................................................... 23 pcon register ................................................................. 123 bor bit ....................................................................... 22 oscf bit..................................................................... 22 por bit ....................................................................... 22 wdton bit ................................................................. 22 picdem 1 low cost picmicro demonstration board ........................................................ 143 picdem 17 demonstration board .................................... 144 picdem 2 low cost pic16cxx demonstration board ........................................................ 143 picdem 3 low cost pic16cxxx demonstration board ........................................................ 144 picstart plus entry level development programmer................................................ 143 pin functions av dd ............................................................................. 9 av ss .............................................................................. 9 ra0/an0/opa+............................................................. 8 ra1/an1/opa- ............................................................. 8 ra2/an2/v ref 2 ............................................................ 8 ra3/an3/v ref 1 ............................................................ 8 ra4/t0cki.................................................................... 8 ra5/mclr /v pp ............................................................. 8 ra6/osc2/clkout/t1cki ......................................... 8 ra7/osc1/clkin......................................................... 8 rb0/int/an4/v r ........................................................... 8 rb1/an5/v dac ............................................................. 8 rb2/an6 ....................................................................... 8 rb3/an7/opa............................................................... 8 rb4 ............................................................................... 8 rb5 ............................................................................... 8 rb6/c1/psmc1a.......................................................... 8 rb7/c2/psmc1b/t1g .................................................. 9 v dd ............................................................................... 9 v ss ................................................................................ 9 pinout description pic16c781/782 ............................................................ 8 pir1 register adif bit ...................................................................... 21 c1if bit....................................................................... 21 c2if bit....................................................................... 21 lvdif bit .................................................................... 21 tmr1if bit ................................................................. 21 plvd dc characteristics.................................................... 163 plvd example ................................................................... 67 pmcon1 ............................................................................ 47 pmdath and pmdatl registers...................................... 47 pmr associated register summary ................................... 50 pointer, fsr ....................................................................... 23 por. see power-on reset porta associated register summary ................................... 34 initialization................................................................. 26 porta and the trisa register ........................................ 26 portb associated register summary ................................... 45 initialization................................................................. 35 pull-up enable (rbpu bit).......................................... 18 rb0/int edge select (intedg bit) ........................... 18 rb0/int pin, external .............................................. 128 rb7:rb0 interrupt-on-change enable (rbie bit).................................................................. 129 rb7:rb4 interrupt-on-change ................................. 129 rb7:rb4 interrupt-on-change flag (rbif bit).................................................................. 129 portb and the trisb register ........................................ 35 portb interrupt-on-change .............................................. 35 portb weak pull-up ......................................................... 35 postscaler, wdt................................................................. 52 assignment (psa bit) ........................................... 18, 52 rate select (ps bits)............................................ 18, 52 switching between timer0 and wdt ......................... 52 power-down mode. see sleep power-on reset (por)..................... 117, 121, 122, 125, 126 oscillator start-up timer (ost) ................................ 117 power control (pcon) register............................... 123 power-down (pd bit) .................................................. 17 power-on reset circuit, external ............................. 122 power-up timer (pwrt) .................................. 117, 122 time-out (to bit) ........................................................ 17 time-out sequence .................................................. 122 time-out sequence on power-up ..................... 125, 127 prescaler, timer0 ............................................................... 52 assignment (psa bit) ........................................... 18, 52 rate select (ps bits)............................................ 18, 52 switching between timer0 and wdt ......................... 52 prescaler, timer1 select (t1ckps1:t1ckps0 bits) .............................. 57 pro mate ii universal device programmer ................... 143 program .............................................................................. 47 program counter pcl register .............................................................. 23 pclath register ............................................... 23, 129 reset conditions ...................................................... 125 program memory paging ........................................................................ 23 program memory map and stack pic16c781 ................................................................. 11 PIC16C782 ................................................................. 11 program memory organization........................................... 11
pic16c781/782 ds41171a-page 178 preliminary ? 2001 microchip technology inc. program memory read (pmr) ........................................... 47 program memory read cycle execution ............................ 50 programmable brown-out reset (pbor) ................. 121, 122 programmable low voltage detect module (plvd).................................................................... 63 control register .......................................................... 63 effects of a reset ..................................................... 67 operation .................................................................... 64 operation during sleep ............................................ 67 programmable switch mode controller (psmc)................. 99 programming c1 for psmc feedback................................ 96 programming, device instructions .................................... 133 psmc associated registers ................................................ 115 configuration............................................................. 107 control registers ...................................................... 104 effects of sleep and reset................................... 115 psmc1a operation in psm mode using c1 comparator only ......................................................... 102 psmc1a output sequence in psm mode using c1 and c2 comparators ......................................... 103 psmc1a output sequence in pwm mode using c1 and c2 comparators ......................................... 101 psmc1a output sequence in pwm mode using c1 comparator only ............................................... 100 psmccon0 register ....................................................... 104 psmccon1 register ....................................................... 104 pulse skip modulation (psm) ........................................... 102 pulse width modulation (pwm) .......................................... 99 r read with code protect set................................................ 50 reading the eprom program memory.............................. 49 registers adc control register (adcon1) ............................... 71 adc control register 0 (adcon0) ............................ 70 adc result register (adres) ................................... 71 analog select .............................................................. 25 calibration control register (calcon) ..................... 85 comparator c1 control register0 (cm1con0) ................................................................ 91 comparator c2 control register0 (cm2con0) ................................................................ 93 comparator c2 control register1 (cm2con1) ................................................................ 94 digital-to-analog converter control register0 (dacon)..................................................................... 79 digital-to-analog converter register (dac) ............... 79 intcon ...................................................................... 19 interrupt-on-change portb ...................................... 36 opamp control register (opacon).......................... 84 option_reg............................................................. 18 pcon.......................................................................... 22 pie1 ............................................................................ 20 program memory address high (pmadrh)............... 48 program memory address low (pmadrl) ................ 48 program memory data high (pmdath) ..................... 47 program memory data low (pmdatl) ...................... 48 program memory read control register 1 (pmcon1) .................................................................. 47 programmable low voltage detect register (lvdcon) ................................................................... 66 psmc control register0 (psmccon0)................... 105 psmc control register1 (psmccon1)................... 106 status ...................................................................... 17 timer1 control register (t1con) .............................. 57 voltage reference control register (refcon)......... 61 weak pull-up portb ................................................. 36 registers associated with vr............................................. 61 registers/bits associated with adc ................................... 77 reset ................................................................................ 121 brown-out reset (bor). see brown-out reset (bor) power-on reset (por). see power-on reset (por) reset conditions for pcon register ....................... 125 reset conditions for program counter..................... 125 reset conditions for status register .................... 125 wdt reset. see watchdog timer (wdt) s setting up the plvd module .............................................. 65 single or dual output ....................................................... 103 sleep .............................................................. 117, 121, 131 slope compensation ........................................................ 103 slope compensation (sc) switch operation.................... 103 software simulator (mplab sim) .................................... 142 special features of the cpu ............................................ 117 special function registers ................................................. 13 adcon0 register ...................................................... 13 adcon1 register ...................................................... 14 adres register ......................................................... 13 ansel register.......................................................... 14 calcon register ...................................................... 15 cm1con0 register.................................................... 15 cm2con0 register.................................................... 15 cm2con1 register.................................................... 15 dac register.............................................................. 15 dacon0 register ...................................................... 15 fsr register .................................................. 13, 14, 16 indf register ........................................... 13, 14, 15, 16 intcon register...................................... 13, 14, 15, 16 iocb register............................................................. 14 lvdcon register....................................................... 14 opacon register ...................................................... 15 option_reg register........................................ 14, 16 pcl register ............................................ 13, 14, 15, 16 pclath register ..................................... 13, 14, 15, 16 pcon register ........................................................... 14 pie1 register ............................................................. 14 pir1 register ............................................................. 13 pmadrh register...................................................... 15 pmadrl register ...................................................... 15 pmcon1 register ...................................................... 16 pmdath register ...................................................... 15 pmdatl register ....................................................... 15 porta register ......................................................... 13 portb register ................................................... 13, 15 psmccon0 register ................................................. 15 psmccon1 register ................................................. 15 refcon register ...................................................... 14 status register...................................... 13, 14, 15, 16 summary .................................................................... 13 t1con register ......................................................... 13 tmr0 register...................................................... 13, 15 tmr1h register ......................................................... 13 tmr1l register.......................................................... 13 trisa register........................................................... 14 trisb register..................................................... 14, 16 wpub register........................................................... 14 stack................................................................................... 23 status register ............................................................. 129
? 2001 microchip technology inc. preliminary ds41171a-page 179 pic16c781/782 c bit ............................................................................ 17 dc bit.......................................................................... 17 irp bit......................................................................... 17 pd bit.......................................................................... 17 rp bits ........................................................................ 17 to bit.......................................................................... 17 zero bit ....................................................................... 17 t t1con register t1ckps1:t1ckps0 bits ............................................ 57 t1oscen bit.............................................................. 57 tmr1cs bit ................................................................ 57 tmr1on bit................................................................ 57 t ad vs. device operating frequencies............................... 72 timer0 ................................................................................. 51 associated registers .................................................. 53 clock source edge select (t0se bit)......................... 51 clock source select (t0cs bit)............................ 18, 51 overflow flag (t0if bit)............................................ 129 overflow interrupt ............................................... 52, 129 prescaler. see prescaler, timer0 timer0 module .................................................................... 51 timer0 operation ................................................................ 51 timer1 associated registers summary.................................. 59 clock source select (tmr1cs bit) ............................ 57 effects of a reset ..................................................... 59 module on/off (tmr1on bit) ..................................... 57 oscillator enable (t1oscen bit) ............................... 57 timer1 incrementing edge.................................................. 58 timer1 initialization ............................................................. 55 timer1 interrupt .................................................................. 59 timer1 module timer/counter ............................................ 55 timer1 module with gate control ....................................... 55 timer1 operation ................................................................ 55 timer1 oscillator for the pic16c781/782 ........................... 59 timing diagrams adc conversion ....................................................... 165 brown-out reset ....................................................... 154 clkout and i/o....................................................... 152 external clock........................................................... 153 external clock timing ............................................... 152 reset, watchdog timer, oscillator start-up timer and power-up timer.................................................. 154 time-out sequence on power-up ..................... 125, 127 timer0 ....................................................................... 156 timer0 and timer1 external clock............................ 156 timer1 ....................................................................... 156 wake-up from sleep via interrupt ........................... 132 trisa, ansel, and control precedence ........................... 26 trisb, ansel, and control precedence ........................... 36 typical low voltage detect application .............................. 63 v voltage reference module effects of a reset..................................................... 61 voltage reference module (vr)......................................... 61 w w register ........................................................................ 129 wake-up from sleep............................................... 117, 131 interrupts .......................................................... 125, 126 mclr reset ............................................................. 126 timing diagram ........................................................ 132 wdt reset ............................................................... 126 watchdog timer associated register summary ................................. 130 watchdog timer (wdt)............................................ 117, 129 enable (wdte bit) ................................................... 129 postscaler. see postscaler, wdt programming considerations ................................... 129 rc oscillator ............................................................ 129 time-out period ........................................................ 129 wdt reset, normal operation................. 121, 125, 126 wdt reset, sleep ......................................... 125, 126 window comparator with interrupt ..................................... 96 www, on-line support ....................................................... 3
pic16c781/782 ds41171a-page 180 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41171a-page181 pic16c781/782 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip ? s development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development sys- tems, technical information and more listing of seminars and events 013001
pic16c781/782 ds41171a-page182 preliminary ? 2001 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41171a pic16c781/782
? 2001 microchip technology inc. preliminary ds41171a-page 183 pic16c781/782 pic16c781/782 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. sales and support part no. x /xx xxx pattern package temperature range device device pic16c781: v dd range 4.0v-5.5v pic16c781t: v dd range 4.0v-5.5v (tape and reel) pic16lc781: v dd range 2.7v-5.5v pic16lc781t: v dd range 2.7v-5.5v (tape and reel) temperature range i = -40 c to +85 c package so = soic ss = ssop p=pdip jw = windowed cerdip pattern qtp, sqtp, rom code (factory specified) or special requirements . blank for otp and windowed devices. examples: a) pic16c781-i/p industrial temp., plastic dip package, normal v dd limits b) pic16lc781-i/ss industrial temp., ssop package, extended v dd limits c) pic16c781-i/sot industrial temp., soic package, tape and reel, normal v dd limits data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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